View ST72T511R9T7S_277210.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ST72311R, ST72511R, ST72532R
8-BIT MCU WITH NESTED INTERRUPTS, EEPROM, ADC, 16-BIT TIMERS, 8-BIT PWM ART, SPI, SCI, CAN INTERFACES
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Memories - 16K to 60K bytes Program memory (ROM,OTP and EPROM) with read-out protection - 256 bytes E2PROM Data memory (only on ST72532R4) - 1024 to 2048 bytes RAM Clock, Reset and Supply Management - Enhanced reset system - Low voltage supply supervisor - Clock sources: crystal/ceramic resonator oscillator or external clock - Beep and Clock-out capability - 4 Power Saving Modes: Halt, Active-Halt, Wait and Slow Interrupt Management - Nested interrupt controller - 13 interrupt vectors plus TRAP and RESET - 15 external interrupt lines (on 4 vectors) - TLI dedicated top level interrupt pin 48 I/O Ports - 48 multifunctional bidirectional I/O lines - 32 alternate function lines - 12 high sink outputs 5 Timers - Configurable watchdog timer - Real time clock timer - One 8-bit auto-reload timer with 4 independent PWM output channels, 2 output compares and external clock with event detector (except on ST725x2R4)
TQFP64 14 x 14
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- Two 16-bit timers with: 2 input captures, 2 output compares, external clock input on one timer, PWM and Pulse generator modes 3 Communications Interfaces - SPI synchronous serial interface - SCI asynchronous serial interface - CAN interface (except on ST72311Rx) 1 Analog peripheral - 8-bit ADC with 8 input channels Instruction Set - 8-bit data manipulation - 63 basic instructions - 17 main addressing modes - 8 x 8 unsigned multiply instruction - True bit manipulation Development Tools - Full hardware/software development package
ST72T311R9 60K 2048 (256) ST72T311R7 48K 1536 (256) ST72T311R6 32K 1024 (256) ST72T532R4
Device Summary
Features Program memory - bytes RAM (stack) - bytes EEPROM - bytes Peripherals Operating Supply CPU Frequency Operating Temperature Packages ST72T511R9 60K 2048 (256) ST72T511R7 48K 1536 (256) ST72T511R6 32K 1024 (256) 16K 1024 (256) 256 Watchdog, two Watchdog, two 16-bit timers, 8-bit PWM ART, Watchdog, two 16-bit timers, 8-bit PWM ART, 16-bit timers, SPI, SCI, CAN, ADC SPI, SCI, ADC SPI, SCI, CAN, ADC 3.0V to 5.5V 3.0 to 5.5V 1) 2 to 8 MHz (with 4 to 16 MHz oscillator) 2 to 4 MHz 1) -40C to +85C (-40C to +105/125C optional) TQFP64
Note 1. See Section 12.3.1 on page 119 for more information on VDD versus fOSC.
Rev. 2.7
April 2003 1/152
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Table of Contents
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2 1.3 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2 EPROM PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3 DATA EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2 3.3 3.4 3.5 3.6 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 MEMORY ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 ACCESS ERROR HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2 4.3 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1 LOW VOLTAGE DETECTOR (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.2 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 25 26 26 26 27 5.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.2 Asynchronous External RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.3 Internal Low Voltage Detection RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.4 Internal Watchdog RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 LOW CONSUMPTION OSCILLATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.2 6.3 6.4 6.5 MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.2 7.3 7.4 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 ACTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 36 37 38 38
7.4.1 ACTIVE-HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.2 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.2.1 Input Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 . 38 ... 8.2.2 Output Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.2.3 Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
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8.3 8.4 8.5 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.5.1 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9 MISCELLANEOUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.1 I/O PORT INTERRUPT SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.2 9.3 I/O PORT ALTERNATE FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 MISCELLANEOUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
10 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.4 Hardware Watchdog Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER (MCC/RTC) . . . . . . . 10.2.1 Programmable CPU Clock Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.2 Clock-out Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.3 Real Time Clock Timer (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3 PWM AUTO-RELOAD TIMER (ART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.3 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.6 Summary of Timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.6 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 49 49 50 50 50 50 52 52 52 52 53 53 53 54 54 55 58 61 61 61 61 73 73 73 74 79 79 79 79 81 88 88 89 92
10.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
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10.6.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 10.6.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 10.6.4 LIN Protocol support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 10.6.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 10.6.6 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 10.6.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 10.6.8 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 10.7 8-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 10.7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.7.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.7.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.7.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.7.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.7.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.7 Relative mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 107 107 108 108 109 111 111 112 112 112 112 112 113 113 114
12 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 12.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 12.1.1 Minimum and Maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.1 Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.2 Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 117 117 117 117 118 118 118 118 119
12.3.1 General Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 12.3.2 Operating Conditions with Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . . 120 12.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 12.4.1 RUN and SLOW Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 12.4.2 WAIT and SLOW WAIT Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 12.4.3 HALT and ACTIVE-HALT Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 12.4.4 Supply and Clock Managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 12.4.5 On-Chip Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 12.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 152 12.5.1 General Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 12.5.2 External Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
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12.5.3 Crystal and Ceramic Resonator Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 12.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 12.6.1 12.6.2 12.6.3 12.7 EMC RAM and Hardware Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EEPROM Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EPROM Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 125 125 126 126 127 129 131
12.7.1 Functional EMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.7.2 Absolute Electrical Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.7.3 ESD Pin Protection Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.8.1 General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 12.8.2 Output Driving Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 12.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 12.9.1 Asynchronous RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 12.9.2 VPP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 12.10 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 12.10.1Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.10.28-Bit PWM-ART Auto-Reload Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.10.316-Bit Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.11 COMMUNICATIONS INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . 12.11.1SPI - Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.11.2SCI - Serial Communications Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.11.3CAN - Controller Area Network Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.12 8-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 134 134 135 135 137 137 138
13 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 13.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 13.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 13.3 SOLDERING AND GLUEABILITY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 14 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 144 14.1 OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 14.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . 145 14.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 14.3.1 Package/socket Footprint Proposal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 14.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 15 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
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1 GENERAL DESCRIPTION
1.1 INTRODUCTION The ST72311R, ST72511R, and ST72532R devices are members of the ST7 microcontroller family. They can be grouped as follows: - ST725xxR devices are designed for mid-range applications with a CAN bus interface (Controller Area Network). These devices are available in OTP and EPROM versions only. - ST72311R devices target the same range of applications but without the CAN interface. These devices are available in ROM, OTP and EPROM versions. All devices are based on a common industrystandard 8-bit core, featuring an enhanced instruction set. Figure 1. Device Block Diagram
8-BIT CORE ALU RESET VPP TLI VDD VSS OSC1 OSC2 CONTROL RAM (1024, 2048 Bytes) LVD OSC EEPROM (256 Bytes)
Under software control, all devices can be placed in WAIT, SLOW, ACTIVE-HALT or HALT mode, reducing power consumption when the application is in idle or standby state. The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. In addition to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes.
PROGRAM MEMORY (16K - 60K Bytes)
ADDRESS AND DATA BUS
MCC/RTC
WATCHDOG PORT A PORT B PB7:0 (8-BIT) PWM ART PORT C TIMER B SPI PC7:0 (8-BIT) PA7:0 (8-BIT)
PORT F PF7:0 (8-BIT) TIMER A BEEP PORT E PE7:0 (8-BIT) CAN SCI PORT D PD7:0 (8-BIT) 8-BIT ADC VDDA VSSA
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1.2 PIN DESCRIPTION Figure 2. 64-Pin TQFP Package Pinout
(HS) PE4 (HS) PE5 (HS) PE6 (HS) PE7 PWM3 / PB0 PWM2 / PB1 PWM1 / PB2 PWM0 / PB3 ARTCLK / PB4 PB5 PB6 PB7 AIN0 / PD0 AIN1 / PD1 AIN2 / PD2 AIN3 / PD3
64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
PE3 / CANRX PE2 / CANTX PE1 / RDI PE0 / TDO VDD_2 OSC1 OSC2 VSS_2 TLI nc RESET VPP PA7 (HS) PA6 (HS) PA5 (HS) PA4 (HS) 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 ei0 44 43 ei2 42 41 40 39 ei3 38 37 36 35 ei1 34 33 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VSS_1 VDD_1 PA3 PA2 PA1 PA0 PC7 / SS PC6 / SCK PC5 / MOSI PC4 / MISO PC3 (HS) / ICAP1_B PC2 (HS) / ICAP2_B PC1 / OCMP1_B PC0 / OCMP2_B VSS_0 VDD_0
AIN4 / PD4 AIN5 / PD5 AIN6 / PD6 AIN7 / PD7 VDDA VSSA VDD_3 VSS_3 MCO / PF0 BEEP / PF1 PF2 OCMP2_A / PF3 OCMP1_A / PF4 ICAP2_A / PF5 ICAP1_A / (HS) PF6 EXTCLK_A / (HS) PF7 (HS) 20mA high sink capability eix associated external interrupt vector
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PIN DESCRIPTION (Cont'd) For external pin connection guidelines, refer to Section 12 "ELECTRICAL CHARACTERISTICS" on page 117. Legend / Abbreviations for Table 1: Type: I = input, O = output, S = supply Input level: A = Dedicated analog input In/Output level: C = CMOS 0.3VDD/0.7VDD, CT= CMOS 0.3VDD/0.7VDD with input trigger Output level: HS = 20mA high sink (on N-buffer only) Port and control configuration: - Input: float = floating, wpu = weak pull-up, int = interrupt 1), ana = analog - Output: OD = open drain 2), PP = push-pull Refer to Section 8 "I/O PORTS" on page 38 for more details on the software configuration of the I/O ports. The RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is in reset state. Table 1. Device Pin Description
Pin n TQFP64 Type Pin Name Level Output Input Port Input float wpu ana int Output OD PP Main function (after reset) Port E4 Port E5 Port E6 Port E7 Port B0 Port B1 Port B2 Port B3 Port B4 Port B5 Port B6 Port B7 Port D0 Port D1 Port D2 Port D3 Port D4 Port D5 Port D6 Port D7 ADC Analog Input 0 ADC Analog Input 1 ADC Analog Input 2 ADC Analog Input 3 ADC Analog Input 4 ADC Analog Input 5 ADC Analog Input 6 ADC Analog Input 7 PWM Output 3 PWM Output 2 PWM Output 1 PWM Output 0 PWM-ART External Clock
Alternate function
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
PE4 (HS) PE5 (HS) PE6 (HS) PE7 (HS) PB0/PWM3 PB1/PWM2 PB2/PWM1 PB3/PWM0 PB4/ARTCLK PB5 PB6 PB7 PD0/AIN0 PD1/AIN1 PD2/AIN2 PD3/AIN3 PD4/AIN4 PD5/AIN5 PD6/AIN6 PD7/AIN7 VDDA VSSA VDD_3
I/O CT HS I/O CT HS I/O CT HS I/O CT HS I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O S S S CT CT CT CT CT CT CT CT CT CT CT CT CT CT CT CT
X X X X X X X X X X X X X X X X X X X X
X X X X ei2 ei2 ei2 ei2 ei3 ei3 ei3 ei3 X X X X X X X X X X X X X X X X
X X X X X X X X X X X X X X X X X X X X
X X X X X X X X X X X X X X X X X X X X
Analog Power Supply Voltage Analog Ground Voltage Digital Main Supply Voltage
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Pin n TQFP64 Type Pin Name
Level Output Input
Port Input float wpu ana int Output OD PP
Main function (after reset)
Alternate function
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
VSS_3 PF0/MCO PF1/BEEP PF2 PF3/OCMP2_A PF4/OCMP1_A PF5/ICAP2_A PF6 (HS)/ICAP1_A VDD_0 VSS_0 PC0/OCMP2_B PC1/OCMP1_B PC2 (HS)/ICAP2_B PC3 (HS)/ICAP1_B PC4/MISO PC5/MOSI PC6/SCK PC7/SS PA0 PA1 PA2 PA3 VDD_1 VSS_1 PA4 (HS) PA5 (HS) PA6 (HS) PA7 (HS) VPP RESET NC NMI VSS_3 OSC2 3) OSC1 3) VDD_3
S I/O I/O I/O I/O I/O I/O CT CT CT CT CT CT X X X X X X X X X X X X X ei1 ei1 ei1 X X X X X X X X X X X X X X X X
Digital Ground Voltage Port F0 Port F1 Port F2 Port F3 Port F4 Port F5 Port F6 Port F7 Timer A Output Compare 2 Timer A Output Compare 1 Timer A Input Capture 2 Timer A Input Capture 1 Timer A External Clock Source Main clock output (fOSC/2) Beep signal output
I/O CT HS S S I/O I/O CT CT
PF7 (HS)/EXTCLK_A I/O CT HS
Digital Main Supply Voltage Digital Ground Voltage X X X X X X X X X X X X X X X X X X X X ei0 ei0 ei0 ei0 X X X X X X X X X X X X X X X X X X X X X X X X Port C0 Port C1 Port C2 Port C3 Port C4 Port C5 Port C6 Port C7 Port A0 Port A1 Port A2 Port A3 Digital Main Supply Voltage Digital Ground Voltage X X X X X X X X T T X X Port A4 Port A5 Port A6 Port A7 Must be tied low in user mode. In programming mode when available, this pin acts as the programming voltage input VPP . C CT X X X Top priority non maskable interrupt (active low) Non maskable interrupt input pin Digital Ground Voltage External clock mode input pull-up or crystal/ceramic resonator oscillator inverter output External clock input or crystal/ceramic resonator oscillator inverter input Digital Main Supply Voltage Timer B Output Compare 2 Timer B Output Compare 1 Timer B Input Capture 2 Timer B Input Capture 1 SPI Master In / Slave Out Data SPI Master Out / Slave In Data SPI Serial Clock SPI Slave Select (active low)
I/O CT HS I/O CT HS I/O I/O I/O I/O I/O I/O I/O I/O S S I/O CT HS I/O CT HS I/O CT HS I/O CT HS I I/O I S I/O I S CT CT CT CT CT CT CT CT
Not Connected
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Pin n TQFP64 Type Pin Name
Level Output Input
Port Input float wpu ana int Output OD PP
Main function (after reset) Port E0 Port E1 Port E2 Port E3
Alternate function
61 62 63 64
PE0/TDO PE1/RDI PE2/CANTX PE3/CANRX
I/O I/O I/O I/O
CT CT CT CT
X X X
X X X X
X X X
X X X
SCI Transmit Data Out SCI Receive Data In CAN Transmit Data Output CAN Receive Data Input
Notes: 1. In the interrupt input column, "eiX" defines the associated external interrupt vector. If the weak pull-up column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input, else the configuration is floating interrupt input. 2. In the open drain output column, "T" defines a true open drain I/O (P-Buffer and protection diode to VDD are not implemented). See Section 8 "I/O PORTS" on page 38 and Section 12.8 "I/O PORT PIN CHARACTERISTICS" on page 131 for more details. 3. OSC1 and OSC2 pins connect a crystal/ceramic resonator or an external source to the on-chip oscillator see Section 1.2 "PIN DESCRIPTION" on page 7 and Section 12.5 "CLOCK AND TIMING CHARACTERISTICS" on page 124 for more details.
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1.3 REGISTER & MEMORY MAP As shown in the Figure 3, the MCU is capable of addressing 64K bytes of memories and I/O registers. The available memory locations consist of 128 bytes of register location, up to 2Kbytes of RAM, up to 256 bytes of data EEPROM and up to Figure 3. Memory Map
0000h 007Fh 0080h
60Kbytes of user program memory. The RAM space includes up to 256 bytes for the stack from 0100h to 01FFh. The highest address bytes contain the user reset and interrupt vectors.
HW Registers (see Table 2) 1024 Bytes RAM 1536 Bytes RAM
0080h
Short Addressing RAM (zero page)
00FFh 0100h
087Fh 0880h 0BFFh 0C00h
2048 Bytes RAM Reserved Optional EEPROM (256 Bytes)
01FFh 0200h
Stack (256 Bytes) 16-bit Addressing RAM
047Fh or 067Fh or 087Fh 1000h
0CFFh 0D00h
Reserved
0FFFh 1000h 4000h
60 KBytes 48 KBytes
Program Memory (60K, 48K, 32K, 16K Bytes)
FFDFh FFE0h FFFFh
8000h
32 KBytes
C000h
Interrupt & Reset Vectors (see Table 7 on page 32)
16 KBytes
FFFFh
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Table 2. Hardware Register Map
Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h to 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h MCC MCCSR MISCR1 SPIDR SPICR SPISR ISPR0 ISPR1 ISPR2 ISPR3 PFDR PFDDR PFOR PDDR PDDDR PDOR PEDR PEDDR PEOR PBDR PBDDR PBOR PCDR PCDDR PCOR Block Register Label PADR PADDR PAOR Register Name Port A Data Register Port A Data Direction Register Port A Option Register Reserved Area (1 Byte) Port C Data Register Port C Data Direction Register Port C Option Register Reserved Area (1 Byte) Port B Data Register Port B Data Direction Register Port B Option Register Reserved Area (1 Byte) Port E Data Register Port E Data Direction Register Port E Option Register Reserved Area (1 Byte) Port D Data Register Port D Data Direction Register Port D Option Register Reserved Area (1 Byte) Port F Data Register Port F Data Direction Register Port F Option Register 00h 1) 00h 00h R/W R/W R/W 00h 1) 00h 00h R/W R/W R/W 00h 1) 00h 00h R/W R/W 2) R/W 2) 00h 1) 00h 00h R/W R/W R/W 00h 1) 00h 00h R/W R/W R/W Reset Status 00h 1) 00h 00h Remarks R/W R/W R/W 2)
Port A
Port C
Port B
Port E
Port D
Port F
Reserved Area (9 Bytes)
Miscellaneous Register 1 SPI Data I/O Register SPI Control Register SPI Status Register Interrupt Software Interrupt Software Interrupt Software Interrupt Software Priority Register 0 Priority Register 1 Priority Register 2 Priority Register 3
00h xxh 0xh 00h FFh FFh FFh FFh
R/W R/W R/W Read Only R/W R/W R/W R/W
SPI
ITC
Reserved Area (1 Byte) Main Clock Control / Status Register 01h R/W
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Address 002Ah 002Bh 002Ch 002Dh to 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h
Block
Register Label WDGCR WDGSR EECSR
Register Name Watchdog Control Register Watchdog Status Register Data EEPROM Control/Status Register
Reset Status 7Fh 000x 000x 00h
Remarks R/W R/W R/W
WATCHDOG EEPROM
Reserved Area (4 Bytes)
TIMER A
TACR2 TACR1 TASR TAIC1HR TAIC1LR TAOC1HR TAOC1LR TACHR TACLR TAACHR TAACLR TAIC2HR TAIC2LR TAOC2HR TAOC2LR MISCR2 TBCR2 TBCR1 TBSR TBIC1HR TBIC1LR TBOC1HR TBOC1LR TBCHR TBCLR TBACHR TBACLR TBIC2HR TBIC2LR TBOC2HR TBOC2LR SCISR SCIDR SCIBRR SCICR1 SCICR2 SCIERPR SCIETPR
Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer
A Control Register 2 A Control Register 1 A Status Register A Input Capture 1 High Register A Input Capture 1 Low Register A Output Compare 1 High Register A Output Compare 1 Low Register A Counter High Register A Counter Low Register A Alternate Counter High Register A Alternate Counter Low Register A Input Capture 2 High Register A Input Capture 2 Low Register A Output Compare 2 High Register A Output Compare 2 Low Register
00h 00h xxh xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h 00h 00h 00h xxh xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h C0h xxh 00xx xxxx xxh 00h 00h 00h
R/W R/W Read Only Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only R/W R/W R/W R/W R/W Read Only Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only R/W R/W Read Only R/W R/W R/W R/W R/W R/W
Miscellaneous Register 2 Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer B Control Register 2 B Control Register 1 B Status Register B Input Capture 1 High Register B Input Capture 1 Low Register B Output Compare 1 High Register B Output Compare 1 Low Register B Counter High Register B Counter Low Register B Alternate Counter High Register B Alternate Counter Low Register B Input Capture 2 High Register B Input Capture 2 Low Register B Output Compare 2 High Register B Output Compare 2 Low Register
TIMER B
SCI
SCI Status Register SCI Data Register SCI Baud Rate Register SCI Control Register 1 SCI Control Register 2 SCI Extended Receive Prescaler Register Reserved area SCI Extended Transmit Prescaler Register
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Address 0058h 0059h 005Ah 005Bh 005Ch 005Dh 005Eh 005Fh 0060h to 006Fh 0070h 0071h 0072h 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007Ah to 007Fh
Block
Register Label
Register Name
Reset Status
Remarks
Reserved Area (2 Bytes) CANISR CANICR CANCSR CANBRPR CANBTR CANPSR CAN Interrupt Status Register CAN Interrupt Control Register CAN Control / Status Register CAN Baud Rate Prescaler Register CAN Bit Timing Register CAN Page Selection Register First address to Last address of CAN page X Data Register Control/Status Register PWM AR Timer Duty Cycle Register 3 PWM AR Timer Duty Cycle Register 2 PWM AR Timer Duty Cycle Register 1 PWM AR Timer Duty Cycle Register 0 PWM AR Timer Control Register Auto-Reload Timer Control/Status Register Auto-Reload Timer Counter Access Register Auto-Reload Timer Auto-Reload Register 00h 00h 00h 00h 23h 00h R/W R/W R/W R/W R/W R/W See CAN Description
CAN
ADC
ADCDR ADCCSR PWMDCR3 PWMDCR2 PWMDCR1 PWMDCR0 PWMCR ARTCSR ARTCAR ARTARR
xxh 00h 00h 00h 00h 00h 00h 00h 00h 00h
Read Only R/W R/W R/W R/W R/W R/W R/W R/W R/W
PWM ART
Reserved Area (6 Bytes)
Legend: x=undefined, R/W=read/write Notes: 1. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents. 2. The bits associated with unavailable pins must always keep their reset value.
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2 EPROM PROGRAM MEMORY
The program memory of the OTP and EPROM devices can be programmed with EPROM programming tools available from STMicroelectronics EPROM Erasure EPROM devices are erased by exposure to high intensity UV light admitted through the transparent window. This exposure discharges the floating gate to its initial state through induced photo current. It is recommended that the EPROM devices be kept out of direct sunlight, since the UV content of sunlight can be sufficient to cause functional failure. Extended exposure to room level fluorescent lighting may also cause erasure. An opaque coating (paint, tape, label, etc...) should be placed over the package window if the product is to be operated under these lighting conditions. Covering the window also reduces IDD in power-saving modes due to photo-diode leakage currents.
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3 DATA EEPROM
3.1 INTRODUCTION The Electrically Erasable Programmable Read Only Memory can be used as a non volatile backup for storing data. Using the EEPROM requires a basic access protocol described in this chapter. 3.2 MAIN FEATURES
s s s s
s s
Up to 16 Bytes programmed in the same cycle EEPROM mono-voltage (charge pump) Chained erase and programming cycles Internal control of the global programming cycle duration End of programming cycle interrupt flag WAIT mode management
Figure 4. EEPROM Block Diagram
EEPROM INTERRUPT
FALLING EDGE DETECTOR
HIGH VOLTAGE PUMP RESERVED EEPROM 0 IE LAT PGM
EECSR
0
0
0
0
ADDRESS DECODER
4
ROW DECODER
EEPROM MEMORY MATRIX (1 ROW = 16 x 8 BITS)
128 DATA MULTIPLEXER 4
128 16 x 8 BITS DATA LATCHES
4
ADDRESS BUS
DATA BUS
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DATA EEPROM (Cont'd) 3.3 MEMORY ACCESS The Data EEPROM memory read/write access modes are controlled by the LAT bit of the EEPROM Control/Status register (EECSR). The flowchart in Figure 5 describes these different memory access modes. Read Operation (LAT=0) The EEPROM can be read as a normal ROM location when the LAT bit of the EECSR register is cleared. In a read cycle, the byte to be accessed is put on the data bus in less than 1 CPU clock cycle. This means that reading data from EEPROM takes the same time as reading data from EPROM, but this memory cannot be used to execute machine code. Note: In order to ensure the correct read out of the EEPROM over the entire temperature range, the cell whose contents will be read, must be read twice in compliance with the following conditions: s a first reading must be immediately followed by a second reading - all interrupts must be disabled until the two readings are performed - no other instructions are allowed between the two reading instructions s the data of the first reading has to be discarded The described procedure corresponds to the following code sequence: sim ld A,eeprom_var ld A,eeprom_var Figure 5. Data EEPROM Programming Flowchart
READ MODE LAT=0 PGM=0 WRITE MODE LAT=1 PGM=0
rim where eeprom_var adresses the EERPOM cell to be read. Any of the ST7 addressing modes may be used. Write Operation (LAT=1) To access the write mode, the LAT bit has to be set by software (the PGM bit remains cleared). When a write access to the EEPROM area occurs, the value is latched inside the 16 data latches according to its address. When PGM bit is set by the software, all the previous bytes written in the data latches (up to 16) are programmed in the EEPROM cells. The effective high address (row) is determined by the last EEPROM write sequence. To avoid wrong programming, the user must take care that all the bytes written between two programming sequences have the same high address: only the four Least Significant Bits of the address can change. At the end of the programming cycle, the PGM and LAT bits are cleared simultaneously, and an interrupt is generated if the IE bit is set. The Data EEPROM interrupt request is cleared by hardware when the Data EEPROM interrupt vector is fetched. Note: Care should be taken during the programming cycle. Writing to the same memory location will over-program the memory (logical AND between the two write access data result) because the data latches are only cleared at the end of the programming cycle and by the falling edge of LAT bit. It is not possible to read the latched data. This note is ilustrated by the Figure 6.
READ BYTES IN EEPROM AREA
WRITE UP TO 16 BYTES IN EEPROM AREA (with the same 12 MSB of the address) START PROGRAMMING CYCLE LAT=1 PGM=1 (set by software)
INTERRUPT GENERATION IF IE=1 CLEARED BY HARDWARE
0
LAT
1
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DATA EEPROM (Cont'd) 3.4 POWER SAVING MODES Wait mode The DATA EEPROM can enter WAIT mode on execution of the WFI instruction of the microcontroller. The DATA EEPROM will immediately enter this mode if there is no programming in progress, otherwise the DATA EEPROM will finish the cycle and then enter WAIT mode. Halt mode The DATA EEPROM immediatly enters HALT mode if the microcontroller executes the HALT instruction. Therefore the EEPROM will stop the function in progress, and data may be corrupted. Figure 6. Data EEPROM Programming Cycle
READ OPERATION NOT POSSIBLE INTERNAL PROGRAMMING VOLTAGE ERASE CYCLE WRITE OF DATA LATCHES WRITE CYCLE READ OPERATION POSSIBLE
3.5 ACCESS ERROR HANDLING If a read access occurs while LAT=1, then the data bus will not be driven. If a write access occurs while LAT=0, then the data on the bus will not be latched. If a programming cycle is interrupted (by software/ RESET action), the memory data will not be guaranteed.
tPROG
LAT
PGM
EEPROM INTERRUPT
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DATA EEPROM (Cont'd) 3.6 REGISTER DESCRIPTION CONTROL/STATUS REGISTER (CSR) Read /Write Reset Value: 0000 0000 (00h)
7 0 0 0 0 0 IE LAT 0 PGM
Bit 1 = LAT Latch Access Transfer This bit is set by software. It is cleared by hardware at the end of the programming cycle. It can only be cleared by software if PGM bit is cleared. 0: Read mode 1: Write mode Bit 0 = PGM Programming control and status This bit is set by software to begin the programming cycle. At the end of the programming cycle, this bit is cleared by hardware and an interrupt is generated if the ITE bit is set. 0: Programming finished or not yet started 1: Programming cycle is in progress Note: if the PGM bit is cleared during the programming cycle, the memory data is not guaranteed
Bits 7:3 = Reserved, forced by hardware to 0. Bit 2 = IE Interrupt enable This bit is set and cleared by software. It enables the Data EEPROM interrupt capability when the PGM bit is cleared by hardware. The interrupt request is automatically cleared when the software enters the interrupt routine. 0: Interrupt disabled 1: Interrupt enabled
Table 3. DATA EEPROM Register Map and Reset Values
Address (Hex.) 002Ch Register Label EECSR Reset Value 0 0 0 0 0 7 6 5 4 3 2 IE 0 1 RWM 0 0 PGM 0
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4 CENTRAL PROCESSING UNIT
4.1 INTRODUCTION This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 4.2 MAIN FEATURES
s s s
4.3 CPU REGISTERS The 6 CPU registers shown in Figure 7 are not present in the memory mapping and are accessed by specific instructions. Accumulator (A) The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. Index Registers (X and Y) These 8-bit registers are used to create effective addresses or as temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.) The Y register is not affected by the interrupt automatic procedures. Program Counter (PC) The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB).
s s s s s
Enable executing 63 basic instructions Fast 8-bit by 8-bit multiply 17 main addressing modes (with indirect addressing mode) Two 8-bit index registers 16-bit stack pointer Low power HALT and WAIT modes Priority maskable hardware interrupts Non-maskable software/hardware interrupts
Figure 7. CPU Registers
7 RESET VALUE = XXh 7 RESET VALUE = XXh 7 RESET VALUE = XXh 15 PCH 87 PCL 0 PROGRAM COUNTER RESET VALUE = RESET VECTOR @ FFFEh-FFFFh 7 0 CONDITION CODE REGISTER 1 1 I1 H I0 N Z C RESET VALUE = 1 1 1 X 1 X X X 15 87 0 STACK POINTER RESET VALUE = STACK HIGHER ADDRESS X = Undefined Value 0 Y INDEX REGISTER 0 X INDEX REGISTER 0 ACCUMULATOR
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CENTRAL PROCESSING UNIT (Cont'd) Condition Code Register (CC) Read/Write Reset Value: 111x1xxx
7
1 1 I1 H I0 N Z
Bit 1 = Z Zero. This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from zero. 1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test instructions. Bit 0 = C Carry/borrow. This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred. This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the "bit test and branch", shift and rotate instructions. Interrupt Management Bits Bit 5,3 = I1, I0 Interrupt The combination of the I1 and I0 bits gives the current interrupt software priority.
Interrupt Software Priority Level 0 (main) Level 1 Level 2 Level 3 (= interrupt disable) I1 1 0 0 1 I0 0 1 0 1
0 C
The 8-bit Condition Code register contains the interrupt masks and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions. These bits can be individually tested and/or controlled by specific instructions. Arithmetic Management Bits Bit 4 = H Half carry. This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instructions. It is reset by hardware during the same instructions. 0: No half carry has occurred. 1: A half carry has occurred. This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines. Bit 2 = N Negative. This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It's a copy of the result 7th bit. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative (i.e. the most significant bit is a logic 1). This bit is accessed by the JRMI and JRPL instructions.
These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (IxSPR). They can be also set/ cleared by software with the RIM, SIM, IRET, HALT, WFI and PUSH/POP instructions. See the interrupt management chapter for more details.
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CENTRAL PROCESSING UNIT (Cont'd) Stack Pointer (SP) Read/Write Reset Value: 01 FFh
15 0 7
SP7 SP6 SP5 SP4 SP3 SP2 SP1
8 0 0 0 0 0 0 1 0 SP0
The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 8). Since the stack is 256 bytes deep, the 8 most significant bits are forced by hardware. Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP7 to SP0 bits are set) which is the stack higher address. Figure 8. Stack Manipulation Example
CALL Subroutine @ 0100h Interrupt Event PUSH Y
The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction. Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow. The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 8. - When an interrupt is received, the SP is decremented and the context is pushed on the stack. - On return from interrupt, the SP is incremented and the context is popped from the stack. A subroutine call occupies two locations and an interrupt five locations in the stack area.
POP Y
IRET
RET or RSP
SP SP CC A X PCH SP PCH @ 01FFh PCL PCL PCH PCL Y CC A X PCH PCL PCH PCL SP CC A X PCH PCL PCH PCL SP PCH PCL SP
Stack Higher Address = 01FFh Stack Lower Address = 0100h
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5 SUPPLY, RESET AND CLOCK MANAGEMENT
The ST72311R, ST72511R and ST72532R microcontrollers include a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components. An overview is shown in Figure 9. Main features s Main supply low voltage detection (LVD) s RESET Manager (RSM) s Low consumption resonator oscillator
Figure 9. Clock, RESET, Option and Supply Management Overview
OSC2 OSCILLATOR OSC1
fOSC
TO MAIN CLOCK CONTROLLER
RESET
RESET
FROM WATCHDOG PERIPHERAL
VDD VSS
LOW VOLTAGE DETECTOR (LVD)
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5.1 LOW VOLTAGE DETECTOR (LVD) To allow the integration of power management features in the application, the Low Voltage Detector function (LVD) generates a static reset when the V DD supply voltage is below a VIT- reference value. This means that it secures the power-up as well as the power-down keeping the ST7 in reset. The VIT- reference value for a voltage drop is lower than the VIT+ reference value for power-on in order to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis). The LVD Reset circuitry generates a reset when VDD is below: - VIT+ when VDD is rising - VIT- when VDD is falling The LVD function is illustrated in Figure 10. Provided the minimum VDD value (guaranteed for the oscillator frequency) is below V IT-, the MCU can only be in two modes: Figure 10. Low Voltage Detector vs Reset
VDD
- under full software control - in static safe reset In these conditions, secure operation is always ensured for the application without the need for external reset hardware. During a Low Voltage Detector Reset, the RESET pin is held low, thus permitting the MCU to reset other devices. Notes: The LVD allows the device to be used without any external RESET circuitry. The LVD is an optional function which can be selected when ordering the device (ordering information).
Vhys VIT+ VIT-
RESET
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5.2 RESET SEQUENCE MANAGER (RSM) 5.2.1 Introduction The reset sequence manager includes three RESET sources as shown in Figure 12: s External RESET source pulse s Internal LVD RESET (Low Voltage Detection) s Internal WATCHDOG RESET These sources act on the RESET pin and it is always kept low during the delay phase. The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory map. The basic RESET sequence consists of 3 phases as shown in Figure 11: s Delay depending on the RESET source s 4096 CPU clock cycle delay s RESET vector fetch Figure 12. Reset Block Diagram The 4096 CPU clock cycle delay allows the oscillator to stabilise and ensures that recovery has taken place from the Reset state. The RESET vector fetch phase duration is 2 clock cycles. Figure 11. RESET Sequence Phases
RESET
DELAY INTERNAL RESET 4096 CLOCK CYCLES FETCH VECTOR
VDD
fCPU
COUNTER
INTERNAL RESET
RON
RESET
WATCHDOG RESET LVD RESET
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RESET SEQUENCE MANAGER (Cont'd) 5.2.2 Asynchronous External RESET pin The RESET pin is both an input and an open-drain output with integrated RON weak pull-up resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled low by external circuitry to reset the device. See electrical characteristics section for more details. A RESET signal originating from an external source must have a duration of at least t h(RSTL)in in order to be recognized as shown in Figure 13. This detection is asynchronous and therefore the MCU can enter reset state even in HALT mode. The RESET pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteristics section. 5.2.3 Internal Low Voltage Detection RESET Two different RESET sequences caused by the internal LVD circuitry can be distinguished: s Power-On RESET s Voltage Drop RESET The device RESET pin acts as an output that is pulled low when VDDFigure 13. RESET Sequences VDD
VIT+ VIT-
WATCHDOG RESET LVD RESET SHORT EXT. RESET
RUN
DELAY
RUN
DELAY
RUN
DELAY
RUN
th(RSTL)in
EXTERNAL RESET SOURCE
tw(RSTL)out
RESET PIN
WATCHDOG RESET WATCHDOG UNDERFLOW INTERNAL RESET (4096 TCPU) FETCH VECTOR
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5.3 LOW CONSUMPTION OSCILLATOR The f OSC main clock of the ST7 can be generated by two different source types: s an external source s a crystal or ceramic resonator oscillators The associated hardware configuration are shown in Table 4. Refer to the electrical characteristics section for more details. External Clock Source In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC1 pin while the OSC2 pin is tied to ground. Crystal/Ceramic Oscillator This oscillator (based on constant current source) is optimized in terms of consumption and has the advantage of producing a very accurate rate on the main clock of the ST7. When using this oscillator, the resonator and the load capacitances have to be connected as shown in Table 4 and have to be mounted as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. This oscillator is not stopped during the RESET phase to avoid losing time in the oscillator start-up phase. These oscillators are not stopped during the RESET phase to avoid losing time in the oscillator start-up phase. Table 4. ST7 Clock Sources
Hardware Configuration
External Clock
ST7 OSC1 OSC2
V DD
EXTERNAL SOURCE
R OBP
Crystal/Ceramic Resonators
ST7 OSC1 OSC2
CL1
LOAD CAPACITORS
CL2
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6 INTERRUPTS
6.1 INTRODUCTION The CPU enhanced interrupt management provides the following features: s Hardware interrupts s Software interrupt (TRAP) s Nested or concurrent interrupt management with flexible interrupt priority and level management: - Up to 4 software programmable nesting levels - Up to 16 interrupt vectors fixed by hardware - 2 non maskable events: RESET, TRAP - 1 maskable Top Level Event: TLI This interrupt management is based on: - Bit 5 and bit 3 of the CPU CC register (I1:0), - Interrupt software priority registers (ISPRx), - Fixed interrupt vector addresses located at the high addresses of the memory map (FFE0h to FFFFh) sorted by hardware priority order. This enhanced interrupt controller guarantees full upward compatibility with the standard (not nested) CPU interrupt controller. 6.2 MASKING AND PROCESSING FLOW The interrupt masking is managed by the I1 and I0 bits of the CC register and the ISPRx registers which give the interrupt software priority level of Figure 14. Interrupt Processing Flowchart
RESET PENDING INTERRUPT N Y TLI Interrupt has the same or a lower software priority than current one N I1:0 Interrupt has a higher software priority than current one Y
each interrupt vector (see Table 1). The processing flow is shown in Figure 1. When an interrupt request has to be serviced: - Normal processing is suspended at the end of the current instruction execution. - The PC, X, A and CC registers are saved onto the stack. - I1 and I0 bits of CC register are set according to the corresponding values in the ISPRx registers of the serviced interrupt vector. - The PC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to "Interrupt Mapping" table for vector addresses). The interrupt service routine should end with the IRET instruction which causes the contents of the saved registers to be recovered from the stack. Note: As a consequence of the IRET instruction, the I1 and I0 bits will be restored from the stack and the program in the previous level will resume. Table 5. Interrupt Software Priority Levels
Interrupt software priority Level 0 (main) Level 1 Level 2 Level 3 (= interrupt disable) Level Low I1 1 0 0 1 I0 0 1 0 1
High
FETCH NEXT INSTRUCTION
THE INTERRUPT STAYS PENDING
Y
"IRET" N
RESTORE PC, X, A, CC FROM STACK
EXECUTE INSTRUCTION
STACK PC, X, A, CC LOAD I1:0 FROM INTERRUPT SW REG. LOAD PC FROM INTERRUPT VECTOR
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INTERRUPTS (Cont'd) Servicing Pending Interrupts As several interrupts can be pending at the same time, the interrupt to be taken into account is determined by the following two-step process: - the highest software priority interrupt is serviced, - if several interrupts have the same software priority then the interrupt with the highest hardware priority is serviced first. Figure 2 describes this decision process. Figure 15. Priority Decision Process
PENDING INTERRUPTS
TRAP (Non Maskable Software Interrupt) This software interrupt is serviced when the TRAP instruction is executed. It will be serviced according to the flowchart in Figure 1 as a TLI. Caution: TRAP can be interrupted by a TLI. s RESET The RESET source has the highest priority in the CPU. This means that the first current routine has the highest software priority (level 3) and the highest hardware priority. See the RESET chapter for more details.
s
Same
SOFTWARE PRIORITY
Different
HIGHEST SOFTWARE PRIORITY SERVICED HIGHEST HARDWARE PRIORITY SERVICED
When an interrupt request is not serviced immediately, it is latched and then processed when its software priority combined with the hardware priority becomes the highest one. Note 1: The hardware priority is exclusive while the software one is not. This allows the previous process to succeed with only one interrupt. Note 2: RESET, TRAP and TLI can be considered as having the highest software priority in the decision process. Different Interrupt Vector Sources Two interrupt source types are managed by the CPU interrupt controller: the non-maskable type (RESET, TRAP) and the maskable type (external or from internal peripherals). Non-Maskable Sources These sources are processed regardless of the state of the I1 and I0 bits of the CC register (see Figure 1). After stacking the PC, X, A and CC registers (except for RESET), the corresponding vector is loaded in the PC register and the I1 and I0 bits of the CC are set to disable interrupts (level 3). These sources allow the processor to exit HALT mode.
Maskable Sources Maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled and if its own interrupt software priority (in ISPRx registers) is higher than the one currently being serviced (I1 and I0 in CC register). If any of these two conditions is false, the interrupt is latched and thus remains pending. s TLI (Top Level Hardware Interrupt) This hardware interrupt occurs when a specific edge is detected on the dedicated TLI pin. Caution: A TRAP instruction must not be used in a TLI service routine. s External Interrupts External interrupts allow the processor to exit from HALT low power mode. External interrupt sensitivity is software selectable through the External Interrupt Control register (EICR). External interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. If several input pins of a group connected to the same interrupt line are selected simultaneously, these will be logically NANDed. s Peripheral Interrupts Usually the peripheral interrupts cause the Device to exit from HALT mode except those mentioned in the "Interrupt Mapping" table. A peripheral interrupt occurs when a specific flag is set in the peripheral status registers and if the corresponding enable bit is set in the peripheral control register. The general sequence for clearing an interrupt is based on an access to the status register followed by a read or write to an associated register. Note: The clearing sequence resets the internal latch. A pending interrupt (i.e. waiting for being serviced) will therefore be lost if the clear sequence is executed.
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INTERRUPTS (Cont'd) 6.3 INTERRUPTS AND LOW POWER MODES All interrupts allow the processor to exit the WAIT low power mode. On the contrary, only external and other specified interrupts allow the processor to exit from the HALT modes (see column "Exit from HALT" in "Interrupt Mapping" table). When several pending interrupts are present while exiting HALT mode, the first one serviced can only be an interrupt with exit from HALT mode capability and it is selected through the same decision process shown in Figure 2. Note: If an interrupt, that is not able to Exit from HALT mode, is pending with the highest priority when exiting HALT mode, this interrupt is serviced after the first one serviced. Figure 16. Concurrent Interrupt Management
SOFTWARE PRIORITY LEVEL TLI IT2 IT1 IT4 IT3 IT0 I1 I0
6.4 CONCURRENT & NESTED MANAGEMENT The following Figure 3 and Figure 4 show two different interrupt management modes. The first is called concurrent mode and does not allow an interrupt to be interrupted, unlike the nested mode in Figure 4. The interrupt hardware priority is given in this order from the lowest to the highest: MAIN, IT4, IT3, IT2, IT1, IT0, TLI. The software priority is given for each interrupt. Warning: A stack overflow may occur without notifying the software of the failure.
HARDWARE PRIORITY
TLI IT0 IT1 IT2 IT3 RIM IT4 MAIN MAIN IT1
3 3 3 3 3 3 3/0 10
11 11 11 11 11 11
11 / 10 Figure 17. Nested Interrupt Management
SOFTWARE PRIORITY LEVEL
TLI
IT2
IT1
IT4
IT3
IT0
I1
I0
HARDWARE PRIORITY
TLI IT0 IT1 IT2 IT3 RIM IT4 MAIN IT4 MAIN IT1 IT2
3 3 2 1 3 3 3/0 10
11 11 00 01 11 11
11 / 10
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USED STACK = 20 BYTES
USED STACK = 10 BYTES
ST72311R, ST72511R, ST72532R
INTERRUPTS (Cont'd) 6.5 INTERRUPT REGISTER DESCRIPTION CPU CC REGISTER INTERRUPT BITS Read /Write Reset Value: 111x 1010 (xAh)
7 1 1 I1 H I0 N Z 0 C ISPR1 I1_7 I0_7 I1_6 I0_6 I1_5 I0_5 I0_9 I1_4 I1_8 I0_4 I0_8
INTERRUPT SOFTWARE PRIORITY REGISTERS (ISPRX) Read/Write (bit 7:4 of ISPR3 are read only) Reset Value: 1111 1111 (FFh)
7 ISPR0 I1_3 I0_3 I1_2 I0_2 I1_1 I0_1 I1_0 0 I0_0
Bit 5, 3 = I1, I0 Software Interrupt Priority These two bits indicate the current interrupt software priority.
Interrupt Software Priority Level 0 (main) Level 1 Level 2 Level 3 (= interrupt disable*) Level Low I1 1 0 0 1 I0 0 1 0 1
ISPR2 ISPR3
I1_11 I0_11 I1_10 I0_10 I1_9 1 1 1 1
I1_13 I0_13 I1_12 I0_12
High
These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (ISPRx). They can be also set/cleared by software with the RIM, SIM, HALT, WFI, IRET and PUSH/POP instructions (see "Interrupt Dedicated Instruction Set" table). *Note: TLI, TRAP and RESET events can interrupt a level 3 program.
These four registers contain the interrupt software priority of each interrupt vector. - Each interrupt vector (except RESET and TRAP) has corresponding bits in these registers where its own software priority is stored. This correspondance is shown in the following table.
Vector address FFFBh-FFFAh FFF9h-FFF8h ... FFE1h-FFE0h ISPRx bits I1_0 and I0_0 bits* I1_1 and I0_1 bits ... I1_13 and I0_13 bits
- Each I1_x and I0_x bit value in the ISPRx registers has the same meaning as the I1 and I0 bits in the CC register. - Level 0 can not be written (I1_x=1, I0_x=0). In this case, the previously stored value is kept. (example: previous=CFh, write=64h, result=44h) The RESET, TRAP and TLI vectors have no software priorities. When one is serviced, the I1 and I0 bits of the CC register are both set. *Note: Bits in the ISPRx registers which correspond to the TLI can be read and written but they are not significant in the interrupt process management. Caution: If the I1_x and I0_x bits are modified while the interrupt x is executed the following behaviour has to be considered: If the interrupt x is still pending (new interrupt or flag not cleared) and the new software priority is higher than the previous one, the interrupt x is re-entered. Otherwise, the software priority stays unchanged up to the next interrupt request (after the IRET of the interrupt x).
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INTERRUPTS (Cont'd) Table 6. Dedicated Interrupt Instruction Set
Instruction HALT IRET JRM JRNM POP CC RIM SIM TRAP WFI New Description Entering Halt mode Interrupt routine return Jump if I1:0=11 Jump if I1:0<>11 Pop CC from the Stack Enable interrupt (level 0 set) Disable interrupt (level 3 set) Software trap Wait for interrupt Pop CC, A, X, PC I1:0=11 ? I1:0<>11 ? Mem => CC Load 10 in I1:0 of CC Load 11 in I1:0 of CC Software NMI I1 1 1 1 1 H I0 0 1 1 0 N Z C Function/Example I1 1 I1 H H I0 0 I0 N Z C N Z C
Note: During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI instructions change the current software priority up to the next IRET instruction or one of the previously mentioned instructions. In order not to lose the current software priority level, the RIM, SIM, HALT, WFI and POP CC instructions should never be used in an interrupt routine.
Table 7. Interrupt Mapping
N Source Block RESET TRAP 0 1 2 3 4 5 6 7 8 9 10 11 12 13 PWM ART TLI MCC/RTC ei0 ei1 ei2 ei3 CAN SPI TIMER A TIMER B SCI EEPROM Reset Software Interrupt External Top Level Interrupt Main Clock Controller Time Base Interrupt External Interrupt Port A3..0 External Interrupt Port F2..0 External Interrupt Port B3..0 External Interrupt Port B7..4 CAN Peripheral Interrupts SPI Peripheral Interrupts TIMER A Peripheral Interrupts TIMER B Peripheral Interrupts SCI Peripheral Interrupts EEPROM Interrupt Not Used PWM ART Overflow Interrupt ARTCSR CANISR SPISR TASR TBSR SCISR EECSR Lowest Priority Yes no N/A Description Register Label N/A MISCR2 MCCSR Priority Order Highest Priority Exit from HALT 1) yes no yes Address Vector FFFEh-FFFFh FFFCh-FFFDh FFFAh-FFFBh FFF8h-FFF9h FFF6h-FFF7h FFF4h-FFF5h FFF2h-FFF3h FFF0h-FFF1h FFEEh-FFEFh FFECh-FFEDh FFEAh-FFEBh FFE8h-FFE9h FFE6h-FFE7h FFE4h-FFE5h FFE2h-FFE3h FFE0h-FFE1h
Note 1: Valid for HALT and ACTIVE-HALT modes except for the MCC/RTC interrupt source which exits from ACTIVE-HALT mode only.
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INTERRUPTS (Cont'd) Table 8. Nested Interrupts Register Map and Reset Values
Address (Hex.) Register Label 7 ei1 0024h ISPR0 Reset Value I1_3 1 SPI 0025h ISPR1 Reset Value I1_7 1 I0_7 1 I1_6 1 SCI I1_10 1 I0_10 1 I0_3 1 I1_2 1 CAN I0_6 1 I1_5 1 6 5 ei0 I0_2 1 4 3 2 1 TLI 1 ei2 I0_5 1 I1_4 1 I0_4 1 1 0
MCC/RTC I1_1 1 ei3 I0_1 1
EEPROM 0026h ISPR2 Reset Value I1_11 1 I0_11 1
TIMER B I1_9 1 I0_9 1
TIMER A I1_8 1 I0_8 1
PWMART 0027h ISPR3 Reset Value 1 1 1 1 I1_13 1 I0_13 1
Not Used I1_12 1 I0_12 1
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7 POWER SAVING MODES
7.1 INTRODUCTION To give a large measure of flexibility to the application in terms of power consumption, four main power saving modes are implemented in the ST7 (see Figure 18): SLOW, WAIT (SLOW WAIT), ACTIVE HALT and HALT. After a RESET the normal operating mode is selected by default (RUN mode). This mode drives the device (CPU and embedded peripherals) by means of a master clock which is based on the main oscillator frequency divided by 2 (f CPU). From RUN mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific ST7 software instruction whose action depends on the oscillator status. Figure 18. Power Saving Mode Transitions
High RUN
fCPU
7.2 SLOW MODE This mode has two targets: - To reduce power consumption by decreasing the internal clock in the device, - To adapt the internal clock frequency (fCPU) to the available supply voltage. SLOW mode is controlled by three bits in the MISCR1 register: the SMS bit which enables or disables Slow mode and two CPx bits which select the internal slow frequency (fCPU). In this mode, the oscillator frequency can be divided by 4, 8, 16 or 32 instead of 2 in normal operating mode. The CPU and peripherals are clocked at this lower frequency. Note: SLOW-WAIT mode is activated when entering the WAIT mode while the device is already in SLOW mode. Figure 19. SLOW Mode Clock Transitions
fOSC/4 fOSC/8 fOSC/2
SLOW
fOSC/2 MISCR1
WAIT SLOW WAIT ACTIVE HALT HALT Low POWER CONSUMPTION
CP1:0 SMS
00
01
NEW SLOW FREQUENCY REQUEST
NORMAL RUN MODE REQUEST
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POWER SAVING MODES (Cont'd) 7.3 WAIT MODE WAIT mode places the MCU in a low power consumption mode by stopping the CPU. This power saving mode is selected by calling the `WFI' instruction. All peripherals remain active. During WAIT mode, the I[1:0] bits of the CC register are forced to `10', to enable all interrupts. All other registers and memory remain unchanged. The MCU remains in WAIT mode until an interrupt or RESET occurs, whereupon the Program Counter branches to the starting address of the interrupt or Reset service routine. The MCU will remain in WAIT mode until a Reset or an Interrupt occurs, causing it to wake up. Refer to Figure 20. Figure 20. WAIT Mode Flow-chart
OSCILLATOR PERIPHERALS CPU I[1:0] BITS ON ON OFF 10
WFI INSTRUCTION
N RESET N INTERRUPT Y OSCILLATOR PERIPHERALS CPU I[1:0] BITS ON OFF ON 10 Y
4096 CPU CLOCK CYCLE DELAY
OSCILLATOR ON PERIPHERALS ON CPU ON XX 1) I[1:0] BITS
FETCH RESET VECTOR OR SERVICE INTERRUPT
Note: 1. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and recovered when the CC register is popped.
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POWER SAVING MODES (Cont'd) 7.4 ACTIVE-HALT AND HALT MODES ACTIVE-HALT and HALT modes are the two lowest power consumption modes of the MCU. They are both entered by executing the `HALT' instruction. The decision to enter either in ACTIVE-HALT or HALT mode is given by the MCC/RTC interrupt enable flag (OIE bit in MCCSR register).
MCCSR OIE bit 0 1 Power Saving Mode entered when HALT instruction is executed HALT mode ACTIVE-HALT mode HALT INSTRUCTION (MCCSR.OIE=1)
Figure 21. ACTIVE-HALT Timing Overview
RUN ACTIVE HALT 4096 CPU CYCLE DELAY RESET OR INTERRUPT RUN
HALT INSTRUCTION [MCCSR.OIE=1]
FETCH VECTOR
Figure 22. ACTIVE-HALT Mode Flow-chart
OSCILLATOR ON PERIPHERALS 1) OFF CPU OFF 10 I[1:0] BITS
7.4.1 ACTIVE-HALT MODE ACTIVE-HALT mode is the lowest power consumption mode of the MCU with a real time clock available. It is entered by executing the `HALT' instruction when the OIE bit of the Main Clock Controller Status register (MCCSR) is set (see Section 10.2 on page 52 for more details on the MCCSR register). The MCU can exit ACTIVE-HALT mode on reception of either an MCC/RTC interrupt, a specific interrupt (see Table 7, "Interrupt Mapping," on page 32) or a RESET. When exiting ACTIVEHALT mode by means of a RESET or an interrupt, a 4096 CPU cycle delay occurs. After the start up delay, the CPU resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see Figure 22). When entering ACTIVE-HALT mode, the I[1:0] bits in the CC register are forced to `10' to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately. In ACTIVE-HALT mode, only the main oscillator and its associated counter (MCC/RTC) are running to keep a wake-up time base. All other peripherals are not clocked except those which get their clock supply from another clock generator (such as external or auxiliary oscillator). The safeguard against staying locked in ACTIVEHALT mode is provided by the oscillator interrupt. Note: As soon as the interrupt capability of one of the oscillators is selected (MCCSR.OIE bit set), entering ACTIVE-HALT mode while the Watchdog is active does not generate a RESET. This means that the device cannot spend more than a defined delay in this power saving mode.
N RESET N INTERRUPT 2) Y OSCILLATOR ON PERIPHERALS OFF CPU ON XX 3) I[1:0] BITS 4096 CPU CLOCK CYCLE DELAY OSCILLATOR ON PERIPHERALS ON CPU ON XX 3) I[1:0] BITS FETCH RESET VECTOR OR SERVICE INTERRUPT Y
Notes: 1. Peripheral clocked with an external clock source can still be active. 2. Only the MCC/RTC interrupt and some specific interrupts can exit the MCU from ACTIVE-HALT mode (such as external interrupt). Refer to Table 7, "Interrupt Mapping," on page 32 for more details. 3. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and restored when the CC register is popped.
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POWER SAVING MODES (Cont'd) 7.4.2 HALT MODE The HALT mode is the lowest power consumption mode of the MCU. It is entered by executing the `HALT' instruction when the OIE bit of the Main Clock Controller Status register (MCCSR) is cleared (see Section 10.2 on page 52 for more details on the MCCSR register). The MCU can exit HALT mode on reception of either a specific interrupt (see Table 7, "Interrupt Mapping," on page 32) or a RESET. When exiting HALT mode by means of a RESET or an interrupt, the oscillator is immediately turned on and the 4096 CPU cycle delay is used to stabilize the oscillator. After the start up delay, the CPU resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see Figure 24). When entering HALT mode, the I bit in the CC register is forced to 0 to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes immediately. In HALT mode, the main oscillator is turned off causing all internal processing to be stopped, including the operation of the on-chip peripherals. All peripherals are not clocked except the ones which get their clock supply from another clock generator (such as an external or auxiliary oscillator). The compatibility of Watchdog operation with HALT mode is configured by the "WDGHALT" option bit of the option byte. The HALT instruction when executed while the Watchdog system is enabled, can generate a Watchdog RESET (see Section 14.1 on page 144 for more details). Figure 23. HALT Timing Overview
RUN HALT 4096 CPU CYCLE DELAY RESET OR INTERRUPT FETCH VECTOR RUN
Figure 24. HALT Mode Flow-chart
HALT INSTRUCTION (MCCSR.OIE=0) ENABLE WDGHALT 1) 1 WATCHDOG RESET OSCILLATOR OFF PERIPHERALS 2) OFF CPU OFF I[1:0] BITS 10 0 WATCHDOG DISABLE
N RESET N Y INTERRUPT 3) Y OSCILLATOR ON PERIPHERALS OFF CPU ON XX 4) I[1:0] BITS 4096 CPU CLOCK CYCLE DELAY OSCILLATOR ON PERIPHERALS ON CPU ON I[1:0] BITS XX 4) FETCH RESET VECTOR OR SERVICE INTERRUPT
HALT INSTRUCTION [MCCSR.OIE=0]
Notes: 1. WDGHALT is an option bit. See option byte section for more details. 2. Peripheral clocked with an external clock source can still be active. 3. Only some specific interrupts can exit the MCU from HALT mode (such as external interrupt). Refer to Table 7, "Interrupt Mapping," on page 32 for more details. 4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and recovered when the CC register is popped.
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8 I/O PORTS
8.1 INTRODUCTION The I/O ports offer different functional modes: - transfer of data through digital inputs and outputs and for specific pins: - external interrupt generation - alternate signal input/output for the on-chip peripherals. An I/O port contains up to 8 pins. Each pin can be programmed independently as digital input (with or without interrupt generation) or digital output. 8.2 FUNCTIONAL DESCRIPTION Each port has 2 main registers: - Data Register (DR) - Data Direction Register (DDR) and one optional register: - Option Register (OR) Each I/O pin may be programmed using the corresponding register bits in the DDR and OR registers: bit X corresponding to pin X of the port. The same correspondence is used for the DR register. The following description takes into account the OR register, (for specific ports which do not provide this register refer to the I/O Port Implementation section). The generic I/O block diagram is shown in Figure 25 8.2.1 Input Modes The input configuration is selected by clearing the corresponding DDR register bit. In this case, reading the DR register returns the digital value applied to the external I/O pin. Different input modes can be selected by software through the OR register. Notes: 1. Writing the DR register modifies the latch value but does not affect the pin status. 2. When switching from input to output mode, the DR register has to be written first to drive the correct level on the pin as soon as the port is configured as an output. 3. Do not use read/modify/write instructions (BSET or BRES) to modify the DR register External interrupt function When an I/O is configured as Input with Interrupt, an event on this I/O can generate an external interrupt request to the CPU. Each pin can independently generate an interrupt request. The interrupt sensitivity is independently programmable using the sensitivity bits in the Miscellaneous register. Each external interrupt vector is linked to a dedicated group of I/O port pins (see pinout description and interrupt section). If several input pins are selected simultaneously as interrupt source, these are logically NANDed. For this reason if one of the interrupt pins is tied low, it masks the other ones. In case of a floating input with interrupt configuration, special care must be taken when changing the configuration (see Figure 26). The external interrupts are hardware interrupts, which means that the request latch (not accessible directly by the application) is automatically cleared when the corresponding interrupt vector is fetched. To clear an unwanted pending interrupt by software, the sensitivity bits in the Miscellaneous register must be modified. 8.2.2 Output Modes The output configuration is selected by setting the corresponding DDR register bit. In this case, writing the DR register applies this digital value to the I/O pin through the latch. Then reading the DR register returns the previously stored value. Two different output modes can be selected by software through the OR register: Output push-pull and open-drain. DR register value and output pin status:
DR 0 1 Push-pull VSS VDD Open-drain Vss Floating
8.2.3 Alternate Functions When an on-chip peripheral is configured to use a pin, the alternate function is automatically selected. This alternate function takes priority over the standard I/O programming. When the signal is coming from an on-chip peripheral, the I/O pin is automatically configured in output mode (push-pull or open drain according to the peripheral). When the signal is going to an on-chip peripheral, the I/O pin must be configured in input mode. In this case, the pin state is also digitally readable by addressing the DR register. Note: Input pull-up configuration can cause unexpected value at the input of the alternate peripheral input. When an on-chip peripheral use a pin as input and output, this pin has to be configured in input floating mode.
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I/O PORTS (Cont'd) Figure 25. I/O Port General Block Diagram
REGISTER ACCESS ALTERNATE OUTPUT 1 VDD 0 ALTERNATE ENABLE DR
P-BUFFER (see table below) PULL-UP (see table below) VDD
DDR PULL-UP CONFIGURATION If implemented OR SEL N-BUFFER DDR SEL CMOS SCHMITT TRIGGER ANALOG INPUT DIODES (see table below) PAD
OR
EXTERNAL INTERRUPT SOURCE (eix)
Table 9. I/O Port Mode Options
Configuration Mode Input Floating with/without Interrupt Pull-up with/without Interrupt Push-pull Open Drain (logic level) True Open Drain Pull-Up Off On Off NI P-Buffer Off On Off NI On On Diodes to VDD to VSS
Output
Legend: NI - not implemented Off - implemented not activated On - implemented and activated
DATA BUS
DR SEL
1 0
ALTERNATE INPUT FROM OTHER BITS
POLARITY SELECTION
NI (see note)
Note: The diode to V DD is not implemented in the true open drain pads. A local protection between the pad and VSS is implemented to protect the device against positive stress.
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I/O PORTS (Cont'd) Table 10. I/O Port Configurations
Hardware Configuration
NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS VDD RPU PAD PULL-UP CONFIGURATION DR REGISTER ACCESS
DR REGISTER
W DATA BUS R
INPUT 1)
ALTERNATE INPUT FROM OTHER PINS INTERRUPT CONFIGURATION POLARITY SELECTION ANALOG INPUT NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS
EXTERNAL INTERRUPT SOURCE (eix)
OPEN-DRAIN OUTPUT 2)
VDD RPU
DR REGISTER ACCESS
PAD
DR REGISTER
R/W
DATA BUS
ALTERNATE ENABLE
ALTERNATE OUTPUT
PUSH-PULL OUTPUT 2)
NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS
VDD RPU
DR REGISTER ACCESS
PAD
DR REGISTER
R/W
DATA BUS
ALTERNATE ENABLE
ALTERNATE OUTPUT
Notes: 1. When the I/O port is in input configuration and the associated alternate function is enabled as an output, reading the DR register will read the alternate function output status. 2. When the I/O port is in output configuration and the associated alternate function is enabled as an input, the alternate function reads the pin status given by the DR register content.
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I/O PORTS (Cont'd) CAUTION: The alternate function must not be activated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts. Analog alternate function When the pin is used as an ADC input, the I/O must be configured as floating input. The analog multiplexer (controlled by the ADC registers) switches the analog voltage present on the selected pin to the common analog rail which is connected to the ADC input. It is recommended not to change the voltage level or loading on any port pin while conversion is in progress. Furthermore it is recommended not to have clocking pins located close to a selected analog pin. WARNING: The analog input voltage level must be within the limits stated in the absolute maximum ratings. 8.3 I/O PORT IMPLEMENTATION The hardware implementation on each I/O port depends on the settings in the DDR and OR registers and specific feature of the I/O port such as ADC Input or true open drain. Switching these I/O ports from one state to another should be done in a sequence that prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 26 Other transitions are potentially risky and should be avoided, since they are likely to present unwanted side-effects such as spurious interrupt generation. Figure 26. Interrupt I/O Port State Transitions
01
INPUT floating/pull-up interrupt
Standard Ports PA5:4, PC7:0, PD7:0, PE7:3, PE1:0, PF7:3
MODE floating input pull-up input open drain output push-pull output DDR 0 0 1 1 OR 0 1 0 1
Interrupt Ports PA2:0, PB7:5, PB2:0, PF1:0 (with pull-up)
MODE floating input pull-up interrupt input open drain output push-pull output DDR 0 0 1 1 OR 0 1 0 1
PA3, PB4, PB3, PF2 (without pull-up)
MODE floating input floating interrupt input open drain output push-pull output DDR 0 0 1 1 OR 0 1 0 1
True Open Drain Ports PA7:6
MODE floating input open drain (high sink ports) DDR 0 1
00
INPUT floating (reset state)
10
OUTPUT open-drain
11
OUTPUT push-pull
Pull-up Input Port (CANTX requirement) PE2
MODE
XX
= DDR, OR
pull-up input
The I/O port register configurations are summarized as follows.
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I/O PORTS (Cont'd) 8.4 LOW POWER MODES
Mode WAIT HALT Description No effect on I/O ports. External interrupts cause the device to exit from WAIT mode. No effect on I/O ports. External interrupts cause the device to exit from HALT mode.
8.5 INTERRUPTS The external interrupt event generates an interrupt if the corresponding configuration is selected with DDR and OR registers and the interrupt mask in the CC register is not active (RIM instruction).
Interrupt Event External interrupt on selected external event Enable Event Control Flag Bit DDRx ORx Exit from Wait Yes Exit from Halt Yes
Table 11. Port Configuration
Input Port Pin name OR = 0 PA7:6 PA5:4 PA3 PA2:0 PB4, PB3 PB7:5, PB2:0 PC7:0 PD7:0 PE7:3, PE1:0 PE2 PF7:3 PF2 PF1:0 floating floating floating floating floating floating floating floating floating floating floating floating OR = 1 OR = 0 OR = 1 High-Sink Yes true open-drain pull-up open drain push-pull floating interrupt open drain push-pull pull-up interrupt open drain push-pull floating interrupt open drain push-pull pull-up interrupt open drain push-pull pull-up open drain push-pull pull-up open drain push-pull pull-up open drain push-pull pull-up input only * pull-up open drain push-pull floating interrupt open drain push-pull pull-up interrupt open drain push-pull Output
Port A
No
Port B Port C Port D Port E
PC3:2 only No PE7:4 only No PF7:6 only No
Port F
* Note: when the CANTX alternate function is selected the IO port operates in output push-pull mode.
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I/O PORTS (Cont'd) 8.5.1 Register Description DATA REGISTER (DR) Port x Data Register PxDR with x = A, B, C, D, E or F. Read /Write Reset Value: 0000 0000 (00h)
7 D7 D6 D5 D4 D3 D2 D1 0 D0
OPTION REGISTER (OR) Port x Option Register PxOR with x = A, B, C, D, E or F. Read /Write Reset Value: 0000 0000 (00h)
7 O7 O6 O5 O4 O3 O2 O1 0 O0
Bit 7:0 = D[7:0] Data register 8 bits. The DR register has a specific behaviour according to the selected input/output configuration. Writing the DR register is always taken into account even if the pin is configured as an input; this allows to always have the expected level on the pin when toggling to output mode. Reading the DR register returns either the DR register latch content (pin configured as output) or the digital value applied to the I/O pin (pin configured as input). DATA DIRECTION REGISTER (DDR) Port x Data Direction Register PxDDR with x = A, B, C, D, E or F. Read /Write Reset Value: 0000 0000 (00h)
7 DD7 DD6 DD5 DD4 DD3 DD2 DD1 0 DD0
Bit 7:0 = O[7:0] Option register 8 bits. For specific I/O pins, this register is not implemented. In this case the DDR register is enough to select the I/O pin configuration. The OR register allows to distinguish: in input mode if the pull-up with interrupt capability or the basic pull-up configuration is selected, in output mode if the push-pull or open drain configuration is selected. Each bit is set and cleared by software. Input mode: 0: floating input 1: pull-up input with or without interrupt Output mode: 0: output open drain (with P-Buffer unactivated) 1: output push-pull
Bit 7:0 = DD[7:0] Data direction register 8 bits. The DDR register gives the input/output direction configuration of the pins. Each bits is set and cleared by software. 0: Input mode 1: Output mode
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I/O PORTS (Cont'd) Table 12. I/O Port Register Map and Reset Values
Address (Hex.) Register Label 7 6 5 4 3 2 1 0
Reset Value of all IO port registers 0000h 0001h 0002h 0004h 0005h 0006h 0008h 0009h 000Ah 000Ch 000Dh 000Eh 0010h 0011h 0012h 0014h 0015h 0016h PADR PADDR PAOR PCDR PCDDR PCOR PBDR PBDDR PBOR PEDR PEDDR PEOR PDDR PDDDR PDOR PFDR PFDDR PFOR
0
0
0
0
0
0
0
0
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
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9 MISCELLANEOUS REGISTERS
The miscellaneous registers allow control over several features such as the external interrupts or the I/Oalternate functions. 9.1 I/O PORT INTERRUPT SENSITIVITY The external interrupt sensitivity is controlled by the IPA, IPB and ISxx bits of the Miscellaneous registers (Figure 27). This control allows to have up to 4 fully independent external interrupt source sensitivities. Each external interrupt source can be generated on four (or five) different events on the pin: s Falling edge s Rising edge s Falling and rising edge s Falling edge and low level s Rising edge and high level (only for ei0 and ei2) To guarantee correct functionality, the sensitivity bits in the MISCR registers must be modified only when the I1 and I0 bits of the CC register are both set to 1 (level 3). See I/O port register and Miscellaneous register descriptions for more details on the programming. 9.2 I/O PORT ALTERNATE FUNCTIONS The MISCR registers allow to manage four I/O port miscellaneous alternate functions: s Main clock signal (fOSC /2) output on PF0 s A Beep signal output on PF1 (with three selectable audio frequencies) s A TLI management on a dedicated pin s A SPI SS pin internal control to use the PC7 I/O port function while the SPI is active. These functions are described in details in the Section 9.3 "MISCELLANEOUS REGISTERS" on page 46.
Figure 27. External Interrupt Sources vs MISCR
PA3 SOURCES PA2 PA1 PA0 SENSITIVITY MISCR2.IPA PF2 SOURCES PF1 PF0 ei1 INTERRUPT SOURCE CONTROL ei0 INTERRUPT SOURCE
MISCR1 IS20 IS21
PB3 SOURCES PB2 PB1 PB0 MISCR2.IPB PB7 SOURCES PB6 PB5 PB4
ei2 INTERRUPT SOURCE
MISCR1 IS10 IS11
SENSITIVITY ei3 INTERRUPT SOURCE CONTROL
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MISCELLANEOUS REGISTERS (Cont'd) 9.3 MISCELLANEOUS REGISTERS MISCELLANEOUS REGISTER 1 (MISCR1) Read /Write Reset Value: 0000 0000 (00h)
7 IS11 IS10 MCO IS21 IS20 CP1 CP0 0 SMS
Bit 4:3 = IS2[1:0] ei0 and ei1 sensitivity The interrupt sensitivity, defined using the IS2[1:0] bits, is applied to the following external interrupts: - ei0 (port A3..0)
External Interrupt Sensitivity IS21 IS20 MISCR2.IPA=0 0 0 1 0 1 0 1 Falling edge & low level Rising edge only Falling edge only MISCR2.IPA=1 Rising edge & high level Falling edge only Rising edge only
Bit 7:6 = IS1[1:0] ei2 and ei3 sensitivity The interrupt sensitivity, defined using the IS1[1:0] bits, is applied to the following external interrupts: - ei2 (port B3..0)
External Interrupt Sensitivity IS11 IS10 MISCR2.IPB=0 0 0 1 1 0 1 0 1 Falling edge & low level Rising edge only Falling edge only MISCR2.IPB=1 Rising edge & high level Falling edge only Rising edge only
1
Rising and falling edge
- ei1 (port F2..0)
IS21 IS20 0 0 1 1 0 1 0 1 External Interrupt Sensitivity Falling edge & low level Rising edge only Falling edge only Rising and falling edge
Rising and falling edge
These 2 bits can be written only when I1 and I0 of the CC register are both set to 1 (level 3). Bit 2:1 = CP[1:0] CPU clock prescaler These bits select the CPU clock prescaler which is applied in the different slow modes. Their action is conditioned by the setting of the SMS bit. These two bits are set and cleared by software
fCPU in SLOW mode fOSC / 4 fOSC / 8 fOSC / 16 fOSC / 32 CP1 0 1 0 1 CP0 0 0 1 1
- ei3 (port B7..4)
IS11 IS10 0 0 1 1 0 1 0 1 External Interrupt Sensitivity Falling edge & low level Rising edge only Falling edge only Rising and falling edge
These 2 bits can be written only when I1 and I0 of the CC register are both set to 1 (level 3). Bit 5 = MCO Main clock out selection This bit enables the MCO alternate function on the PF0 I/O port. It is set and cleared by software. 0: MCO alternate function disabled (I/O pin free for general-purpose I/O) 1: MCO alternate function enabled (f OSC/2on I/O port) Note: To reduce power consumption, the MCO function is not active in ACTIVE-HALT mode.
Bit 0 = SMS Slow mode select This bit is set and cleared by software. 0: Normal mode. fCPU = fOSC / 2 1: Slow mode. fCPU is given by CP1, CP0 See Section 7.2 "SLOW MODE" on page 34 and Section 10.2 "MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER (MCC/RTC)" on page 52 for more details.
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MISCELLANEOUS REGISTERS (Cont'd) MISCELLANEOUS REGISTER 2 (MISCR2) Read /Write Reset Value: 0000 0000 (00h)
7 IPA IPB BC1 BC0 TLIS TLIE SSM 0 SSI
Bit 3 = TLIS TLI sensitivity This bit allows to toggle the TLI edge sensitivity. It can be set and cleared by software only when TLIE bit is cleared. 0: Falling edge 1: Rising edge Bit 2 = TLIE TLI enable This bit allows to enable or disable the TLI capability on the dedicated pin. It is set and cleared by software. 0: TLI disabled 1: TLI enabled Note: a parasitic interrupt can be generated when clearing the TLIE bit. Bit 1 = SSM SS mode selection This bit is set and cleared by software. 0: Normal mode - the level of the SPI SS signal is input from the external SS pin. 1: I/O mode (PC7), the level of the SPI SS signal is read from the SSI bit. Bit 0 = SSI SS internal mode This bit replaces pin SS of the SPI when bit SSM is set to 1. (see SPI description). It is set and cleared by software.
Bit 7 = IPA Interrupt polarity for port A This bit is used to invert the sensitivity of the port A [3:0] external interrupts. It is set and cleared by software. 0: No sensitivity inversion 1: Sensitivity inversion See Section 9.1 "I/O PORT INTERRUPT SENSITIVITY" on page 45 and the description of the IS2x bits of the MISCR1 register for more details. Bit 6 = IPB Interrupt polarity for port B This bit is used to invert the sensitivity of the port B [3:0] external interrupts. It is set and cleared by software. 0: No sensitivity inversion 1: Sensitivity inversion See Section 9.1 "I/O PORT INTERRUPT SENSITIVITY" on page 45 and the description of the IS1x bits of the MISCR1 register for more details. Bit 5:4 = BC[1:0] Beep control These 2 bits select the PF1 pin beep capability.
BC1 0 0 1 1 BC0 0 1 0 1 ~2-KHz ~1-KHz ~500-Hz Beep mode with fOSC=16MHz Off Output Beep signal ~50% duty cycle
The beep output signal is available in ACTIVEHALT mode but has to be disabled to reduce the consumption.
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MISCELLANEOUS REGISTERS (Cont'd) Table 13. Miscellaneous Register Map and Reset Values
Address (Hex.) 0020h 0040h Register Label MISCR1 Reset Value MISCR2 Reset Value 7 IS11 0 IPA 0 6 IS10 0 IPB 0 5 MCO 0 BC1 0 4 IS21 0 BC0 0 3 IS20 0 TLIS 0 2 CP1 0 TLIE 0 1 CP0 0 SSM 0 0 SMS 0 SSI 0
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10 ON-CHIP PERIPHERALS
10.1 WATCHDOG TIMER (WDG) 10.1.1 Introduction The Watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The Watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the counter's contents before the T6 bit becomes cleared. 10.1.2 Main Features s Programmable timer (64 increments of 12288 CPU cycles) s Programmable reset s Reset (if watchdog activated) after a HALT instruction or when the T6 bit reaches zero Figure 28. Watchdog Block Diagram
s s
Hardware Watchdog selectable by option byte Watchdog Reset indicated by status flag (in versions with Safe Reset option only)
10.1.3 Functional Description The counter value stored in the CR register (bits T[6:0]), is decremented every 12,288 machine cycles, and the length of the timeout period can be programmed by the user in 64 increments. If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T[6:0]) rolls over from 40h to 3Fh (T6 becomes cleared), it initiates a reset cycle pulling low the reset pin for typically 500ns.
RESET
WATCHDOG CONTROL REGISTER (CR) WDGA T6
T5
T4
T3
T2
T1
T0
7-BIT DOWNCOUNTER
fCPU
CLOCK DIVIDER /12288
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WATCHDOG TIMER (Cont'd) The application program must write in the CR register at regular intervals during normal operation to prevent an MCU reset. The value to be stored in the CR register must be between FFh and C0h (see Table 14 .Watchdog Timing (fCPU = 8 MHz)): - The WDGA bit is set (watchdog enabled) - The T6 bit is set to prevent generating an immediate reset - The T[5:0] bits contain the number of increments which represents the time delay before the watchdog produces a reset. Table 14.Watchdog Timing (fCPU = 8 MHz)
CR Register initial value Max Min FFh C0h WDG timeout period (ms) 98.304 1.536
10.1.7 Register Description CONTROL REGISTER (CR) Read /Write Reset Value: 0111 1111 (7Fh)
7 WDGA T6 T5 T4 T3 T2 T1 0 T0
Bit 7 = WDGA Activation bit. This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. 0: Watchdog disabled 1: Watchdog enabled Note: This bit is not used if the hardware watchdog option is enabled by option byte. Bit 6:0 = T[6:0] 7-bit timer (MSB to LSB). These bits contain the decremented value. A reset is produced when it rolls over from 40h to 3Fh (T6 becomes cleared). STATUS REGISTER (SR) Read /Write Reset Value*: 0000 0000 (00h)
7 0 WDOGF
Notes: Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except by a reset. The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared). If the watchdog is activated, the HALT instruction will generate a Reset. 10.1.4 Hardware Watchdog Option If Hardware Watchdog is selected by option byte, the watchdog is always active and the WDGA bit in the CR is not used. Refer to the device-specific Option Byte description. 10.1.5 Low Power Modes
Mode WAIT HALT Description No effect on Watchdog.
Bit 0 = WDOGF Watchdog flag. This bit is set by a watchdog reset and cleared by software or a power on/off reset. This bit is useful for distinguishing power/on off or external reset and watchdog reset. 0: No Watchdog reset occurred 1: Watchdog reset occurred * Only by software and power on/off reset Note: This register is not used in versions without LVD Reset.
Immediate reset generation as soon as the HALT instruction is executed if the Watchdog is activated (WDGA bit is set).
10.1.6 Interrupts None.
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WATCHDOG TIMER (Cond't) Table 15. Watchdog Timer Register Map and Reset Values
Address (Hex.) 002Ah 002Bh Register Label WDGCR Reset Value WDGSR Reset Value 7 WDGA 0 0 6 T6 1 0 5 T5 1 0 4 T4 1 0 3 T3 1 0 2 T2 1 0 1 T1 1 0 0 T0 1 WDOGF 0
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10.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER (MCC/RTC) The Main Clock Controller consists of three different functions: s a programmable CPU clock prescaler s a clock-out signal to supply external devices s a real time clock timer with interrupt capability Each function can be used independently and simultaneously. 10.2.1 Programmable CPU Clock Prescaler The programmable CPU clock prescaler supplies the clock for the ST7 CPU and its internal peripherals. It manages SLOW power saving mode (See Section 7.2 "SLOW MODE" on page 34 for more details). The prescaler selects the fCPU main clock frequency and is controlled by three bits in the MISCR1 register: CP[1:0] and SMS. CAUTION: The prescaler does not act on the CAN peripheral clock source. This peripheral is always supplied by the f OSC/2 clock source. 10.2.2 Clock-out Capability The clock-out capability is an alternate function of an I/O port pin that outputs a fOSC/2 clock to drive external devices. It is controlled by the MCO bit in the MISCR1 register. CAUTION: When selected, the clock out pin suspends the clock during ACTIVE-HALT mode. 10.2.3 Real Time Clock Timer (RTC) The counter of the real time clock timer allows an interrupt to be generated based on an accurate real time clock. Four different time bases depending directly on fOSC are available. The whole functionality is controlled by four bits of the MCCSR register: TB[1:0], OIE and OIF. When the RTC interrupt is enabled (OIE bit set), the ST7 enters ACTIVE-HALT mode when the HALT instruction is executed. See Section 7.4 "ACTIVE-HALT AND HALT MODES" on page 36 for more details.
Figure 29. Main Clock Controller (MCC/RTC) Block Diagram
CLOCK TO CAN PERIPHERAL PORT ALTERNATE FUNCTION fOSC/2 MISCR1 MCO CP1 CP0 SMS
MCO
fOSC
DIV 2 RTC COUNTER
DIV 2, 4, 8, 16 fCPU
CPU CLOCK TO CPU AND PERIPHERALS
MCCSR 0 0 0 0 TB1 TB0 OIE OIF
MCC/RTC INTERRUPT
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MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER (Cont'd) 10.2.4 Register Description MISCELLANEOUS REGISTER 1 (MISCR1) See "MISCELLANEOUS REGISTERS" Section. MAIN CLOCK CONTROL/STATUS REGISTER (MCCSR) Read /Write Reset Value: 0000 0001 (01h)
7
0 0 0 0 TB1 TB0 OIE
Bit 0 = OIF Oscillator interrupt flag This bit is set by hardware and cleared by software reading the CSR register. It indicates when set that the main oscillator has reached the selected elapsed time (TB1:0). 0: Timeout not reached 1: Timeout reached CAUTION: The BRES and BSET instructions must not be used on the MCCSR register to avoid unintentionally clearing the OIF bit. 10.2.5 Low Power Modes
0
OIF
Mode
Description No effect on MCC/RTC peripheral. MCC/RTC interrupt cause the device to exit from WAIT mode. No effect on MCC/RTC counter (OIE bit is set), the registers are frozen. MCC/RTC interrupt cause the device to exit from ACTIVE-HALT mode. MCC/RTC counter and registers are frozen. MCC/RTC operation resumes when the MCU is woken up by an interrupt with "exit from HALT" capability.
Bit 7:4 = Reserved, always read as 0. Bit 3:2 = TB[1:0] Time base control These bits select the programmable divider time base. They are set and cleared by software.
Counter Prescaler 32000 64000 160000 400000 Time Base TB1 fOSC =8MHz 4ms 8ms 20ms 50ms fOSC=16MHz 2ms 4ms 10ms 25ms 0 0 1 1 0 1 0 1 TB0
WAIT
ACTIVEHALT
HALT
10.2.6 Interrupts The MCC/RTC interrupt event generates an interrupt if the OIE bit of the MCCSR register is set and the interrupt mask in the CC register is not active (RIM instruction).
Interrupt Event Time base overflow event Enable Event Control Flag Bit OIF OIE Exit from Wait Yes Exit from Halt No 1)
A modification of the time base is taken into account at the end of the current period (previously set) to avoid an unwanted time shift. This allows to use this time base as a real time clock. Bit 1 = OIE Oscillator interrupt enable This bit set and cleared by software. 0: Oscillator interrupt disabled 1: Oscillator interrupt enabled This interrupt can be used to exit from ACTIVEHALT mode. When this bit is set, calling the ST7 software HALT instruction enters the ACTIVE-HALT power saving mode.
Note: 1. The MCC/RTC interrupt allows to exit from ACTIVE-HALT mode, not from HALT mode.
Table 16. MCC/RTC Register Map and Reset Values
Address (Hex.) 0029h Register Label MCCSR Reset Value 7 6 5 4 3 TB1 0 2 TB0 0 1 OIE 0 0 OIF 1
0
0
0
0
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10.3 PWM AUTO-RELOAD TIMER (ART) 10.3.1 Introduction The Pulse Width Modulated Auto-Reload Timer on-chip peripheral consists of an 8-bit auto reload counter with compare capabilities and of a 7-bit prescaler clock source. These resources allow three possible operating modes: - Generation of up to 4 independent PWM signals - Output compare and Time base interrupt - External event detector Figure 30. PWM Auto-Reload Timer Block Diagram
The two first modes can be used together with a single counter frequency. The timer can be used to wake up the MCU from WAIT and HALT modes.
PWMCR
OEx
OPx
OCRx REGISTER LOAD
DCRx REGISTER
PWMx
PORT ALTERNATE FUNCTION
POLARITY CONTROL
COMPARE
ARR REGISTER
8-BIT COUNTER (CAR REGISTER)
LOAD
ARTCLK
fEXT fCPU
fCOUNTER MUX fINPUT
PROGRAMMABLE PRESCALER
EXCL
CC2
CC1
CC0
TCE
FCRL
OIE
OVF
ARTCSR
OVF INTERRUPT
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PWM AUTO-RELOAD TIMER (Cont'd) 10.3.2 Functional Description Counter The free running 8-bit counter is fed by the output of the prescaler, and is incremented on every rising edge of the clock signal. It is possible to read or write the contents of the counter on the fly by reading or writing the Counter Access register (ARTCAR). When a counter overflow occurs, the counter is automatically reloaded with the contents of the ARTARR register (the prescaler is not affected). Counter clock and prescaler The counter clock frequency is given by: fCOUNTER = fINPUT / 2CC[2:0] The timer counter's input clock (fINPUT) feeds the 7-bit programmable prescaler, which selects one of the 8 available taps of the prescaler, as defined by CC[2:0] bits in the Control/Status Register (ARTCSR). Thus the division factor of the prescaler can be set to 2 n (where n = 0, 1,..7). This fINPUT frequency source is selected through the EXCL bit of the ARTCSR register and can be either the f CPU or an external input frequency fEXT. The clock input to the counter is enabled by the TCE (Timer Counter Enable) bit in the ARTCSR register. When TCE is reset, the counter is stopped and the prescaler and counter contents are frozen. When TCE is set, the counter runs at the rate of the selected clock source. Figure 31. Output compare control Counter and Prescaler Initialization After RESET, the counter and the prescaler are cleared and fINPUT = fCPU. The counter can be initialized by: - Writing to the ARTARR register and then setting the FCRL (Force Counter Re-Load) and the TCE (Timer Counter Enable) bits in the ARTCSR register. - Writing to the ARTCAR counter access register, In both cases the 7-bit prescaler is also cleared, whereupon counting will start from a known value. Direct access to the prescaler is not possible. Output compare control The timer compare function is based on four different comparisons with the counter (one for each PWMx output). Each comparison is made between the counter value and an output compare register (OCRx) value. This OCRx register can not be accessed directly, it is loaded from the duty cycle register (PWMDCRx) at each overflow of the counter. This double buffering method avoids glitch generation when changing the duty cycle on the fly.
fCOUNTER ARTARR=FDh COUNTER FDh FEh FFh FDh FEh FFh FDh FEh FFh
OCRx
FDh
FEh
PWMDCRx
FDh
FEh
PWMx
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PWM AUTO-RELOAD TIMER (Cont'd) Independent PWM signal generation This mode allows up to four Pulse Width Modulated signals to be generated on the PWMx output pins with minimum core processing overhead. This function is stopped during HALT mode. Each PWMx output signal can be selected independently using the corresponding OEx bit in the PWM Control register (PWMCR). When this bit is set, the corresponding I/O pin is configured as output push-pull alternate function. The PWM signals all have the same frequency which is controlled by the counter period and the ARTARR register value. fPWM = fCOUNTER / (256 - ARTARR) When a counter overflow occurs, the PWMx pin level is changed depending on the corresponding OPx (output polarity) bit in the PWMCR register. Figure 32. PWM Auto-reload Timer Function
255 DUTY CYCLE REGISTER (PWMDCRx)
When the counter reaches the value contained in one of the output compare register (OCRx) the corresponding PWMx pin level is restored. It should be noted that the reload values will also affect the value and the resolution of the duty cycle of the PWM output signal. To obtain a signal on a PWMx pin, the contents of the OCRx register must be greater than the contents of the ARTARR register. The maximum available resolution for the PWMx duty cycle is: Resolution = 1 / (256 - ARTARR) Note: To get the maximum resolution (1/256), the ARTARR register must be 0. With this maximum resolution, 0% and 100% can be obtained by changing the polarity.
COUNTER
AUTO-RELOAD REGISTER (ARTARR) 000
t
PWMx OUTPUT
WITH OEx=1 AND OPx=0 WITH OEx=1 AND OPx=1
Figure 33. PWM Signal from 0% to 100% Duty Cycle
fCOUNTER ARTARR=FDh COUNTER FDh FEh FFh FDh FEh FFh FDh FEh
OCRx=FCh PWMx OUTPUT WITH OEx=1 AND OPx=0 OCRx=FDh OCRx=FEh OCRx=FFh
t
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PWM AUTO-RELOAD TIMER (Cont'd) Output compare and Time base interrupt On overflow, the OVF flag of the ARTCSR register is set and an overflow interrupt request is generated if the overflow interrupt enable bit, OIE, in the ARTCSR register, is set. The OVF flag must be reset by the user software. This interrupt can be used as a time base in the application. External clock and event detector mode Using the fEXT external prescaler input clock, the auto-reload timer can be used as an external clock event detector. In this mode, the ARTARR register is used to select the nEVENT number of events to be counted before setting the OVF flag. nEVENT = 256 - ARTARR When entering HALT mode while fEXT is selected, all the timer control registers are frozen but the counter continues to increment. If the OIE bit is set, the next overflow of the counter will generate an interrupt which wakes up the MCU.
Figure 34. External Event Detector Example (3 counts)
fEXT=f COUNTER ARTARR=FDh
COUNTER
FDh
FEh
FFh
FDh
FEh
FFh
FDh
OVF
ARTCSR READ INTERRUPT IF OIE=1 INTERRUPT IF OIE=1
ARTCSR READ
t
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PWM AUTO-RELOAD TIMER (Cont'd) 10.3.3 Register Description CONTROL / STATUS REGISTER (ARTCSR) Read /Write Reset Value: 0000 0000 (00h)
7 EXCL CC2 CC1 CC0 TCE FCRL OIE 0 OVF 7 0 CA6 CA5 CA4 CA3 CA2 CA1 CA0
0: New transition not yet reached 1: Transition reached COUNTER ACCESS REGISTER (ARTCAR) Read /Write Reset Value: 0000 0000 (00h)
Bit 7 = EXCL External Clock This bit is set and cleared by software. It selects the input clock for the 7-bit prescaler. 0: CPU clock. 1: External clock. Bit 6:4 = CC[2:0] Counter Clock Control These bits are set and cleared by software. They determine the prescaler division ratio from f INPUT.
fCOUNTER fINPUT fINPUT / 2 fINPUT / 4 fINPUT / 8 fINPUT / 16 fINPUT / 32 fINPUT / 64 fINPUT / 128 With fINPUT=8 MHz CC2 CC1 CC0 8 MHz 4 MHz 2 MHz 1 MHz 500 KHz 250 KHz 125 KHz 62.5 KHz 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
CA7
Bit 7:0 = CA[7:0] Counter Access Data These bits can be set and cleared either by hardware or by software. The ARTCAR register is used to read or write the auto-reload counter "on the fly" (while it is counting).
AUTO-RELOAD REGISTER (ARTARR) Read /Write Reset Value: 0000 0000 (00h)
7 AR7 AR6 AR5 AR4 AR3 AR2 AR1 0 AR0
Bit 3 = TCE Timer Counter Enable This bit is set and cleared by software. It puts the timer in the lowest power consumption mode. 0: Counter stopped (prescaler and counter frozen). 1: Counter running. Bit 2 = FCRL Force Counter Re-Load This bit is write-only and any attempt to read it will yield a logical zero. When set, it causes the contents of ARTARR register to be loaded into the counter, and the content of the prescaler register to be cleared in order to initialize the timer before starting to count. Bit 1 = OIE Overflow Interrupt Enable This bit is set and cleared by software. It allows to enable/disable the interrupt which is generated when the OVF bit is set. 0: Overflow Interrupt disable. 1: Overflow Interrupt enable. Bit 0 = OVF Overflow Flag This bit is set by hardware and cleared by software reading the ARTCSR register. It indicates the transition of the counter from FFh to the ARTARR value.
Bit 7:0 = AR[7:0] Counter Auto-Reload Data These bits are set and cleared by software. They are used to hold the auto-reload value which is automatically loaded in the counter when an overflow occurs. At the same time, the PWM output levels are changed according to the corresponding OPx bit in the PWMCR register. This register has two PWM management functions: - Adjusting the PWM frequency - Setting the PWM duty cycle resolution PWM Frequency vs. Resolution:
ARTARR value 0 [ 0..127 ] [ 128..191 ] [ 192..223 ] [ 224..239 ] Resolution Min 8-bit > 7-bit > 6-bit > 5-bit > 4-bit ~0.244-KHz ~0.244-KHz ~0.488-KHz ~0.977-KHz ~1.953-KHz fPWM Max 31.25-KHz 62.5-KHz 125-KHz 250-KHz 500-KHz
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PWM AUTO-RELOAD TIMER (Cont'd) PWM CONTROL REGISTER (PWMCR) Read /Write Reset Value: 0000 0000 (00h)
7 OE3 OE2 OE1 OE0 OP3 OP2 OP1 0 OP0
DUTY CYCLE REGISTERS (PWMDCRx) Read /Write Reset Value: 0000 0000 (00h)
7 DC7 DC6 DC5 DC4 DC3 DC2 DC1 0 DC0
Bit 7:4 = OE[3:0] PWM Output Enable These bits are set and cleared by software. They enable or disable the PWM output channels independently acting on the corresponding I/O pin. 0: PWM output disabled. 1: PWM output enabled. Bit 3:0 = OP[3:0] PWM Output Polarity These bits are set and cleared by software. They independently select the polarity of the four PWM output signals.
PWMx output level OPx Counter <= OCRx 1 0 Counter > OCRx 0 1 0 1
Bit 7:0 = DC[7:0] Duty Cycle Data These bits are set and cleared by software. A PWMDCRx register is associated with the OCRx register of each PWM channel to determine the second edge location of the PWM signal (the first edge location is common to all channels and given by the ARTARR register). These PWMDCR registers allow the duty cycle to be set independently for each PWM channel.
Note: When an OPx bit is modified, the PWMx output signal polarity is immediately reversed.
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PWM AUTO-RELOAD TIMER (Cont'd) Table 17. PWM Auto-Reload Timer Register Map and Reset Values
Address (Hex.) 0072h Register Label PWMDCR3 Reset Value PWMDCR2 Reset Value PWMDCR1 Reset Value PWMDCR0 Reset Value PWMCR Reset Value ARTCSR Reset Value ARTCAR Reset Value ARTARR Reset Value 7 DC7 0 DC7 0 DC7 0 DC7 0 OE3 0 EXCL 0 CA7 0 AR7 0 6 DC6 0 DC6 0 DC6 0 DC6 0 OE2 0 CC2 0 CA6 0 AR6 0 5 DC5 0 DC5 0 DC5 0 DC5 0 OE1 0 CC1 0 CA5 0 AR5 0 4 DC4 0 DC4 0 DC4 0 DC4 0 OE0 0 CC0 0 CA4 0 AR4 0 3 DC3 0 DC3 0 DC3 0 DC3 0 OP3 0 TCE 0 CA3 0 AR3 0 2 DC2 0 DC2 0 DC2 0 DC2 0 OP2 0 FCRL 0 CA2 0 AR2 0 1 DC1 0 DC1 0 DC1 0 DC1 0 OP1 0 OIE 0 CA1 0 AR1 0 0 DC0 0 DC0 0 DC0 0 DC0 0 OP0 0 OVF 0 CA0 0 AR0 0
0073h
0074h
0075h
0076h
0077h
0078h
0079h
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10.4 16-BIT TIMER 10.4.1 Introduction The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including measuring the pulse lengths of up to two input signals (input capture) or generating up to two output waveforms (output compare and PWM). Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the CPU clock prescaler. Some ST7 devices have two on-chip 16-bit timers. They are completely independent, and do not share any resources. They are synchronized after a MCU reset as long as the timer clock frequencies are not modified. This description covers one or two 16-bit timers. In ST7 devices with two timers, register names are prefixed with TA (Timer A) or TB (Timer B). 10.4.2 Main Features s Programmable prescaler: fCPU divided by 2, 4 or 8. s Overflow status flag and maskable interrupt s External clock input (must be at least 4 times slower than the CPU clock speed) with the choice of active edge s Output compare functions with: - 2 dedicated 16-bit registers - 2 dedicated programmable signals - 2 dedicated status flags - 1 dedicated maskable interrupt s Input capture functions with: - 2 dedicated 16-bit registers - 2 dedicated active edge selection signals - 2 dedicated status flags - 1 dedicated maskable interrupt s Pulse Width Modulation mode (PWM) s One Pulse mode s 5 alternate functions on I/O ports (ICAP1, ICAP2, OCMP1, OCMP2, EXTCLK)* The Block Diagram is shown in Figure 35. *Note: Some timer pins may not be available (not bonded) in some ST7 devices. Refer to the device pin out description. When reading an input signal on a non-bonded pin, the value will always be `1'. 10.4.3 Functional Description 10.4.3.1 Counter The main block of the Programmable Timer is a 16-bit free running upcounter and its associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called high & low. Counter Register (CR): - Counter High Register (CHR) is the most significant byte (MS Byte). - Counter Low Register (CLR) is the least significant byte (LS Byte). Alternate Counter Register (ACR) - Alternate Counter High Register (ACHR) is the most significant byte (MS Byte). - Alternate Counter Low Register (ACLR) is the least significant byte (LS Byte). These two read-only 16-bit registers contain the same value but with the difference that reading the ACLR register does not clear the TOF bit (Timer overflow flag), located in the Status register (SR). (See note at the end of paragraph titled 16-bit read sequence). Writing in the CLR register or ACLR register resets the free running counter to the FFFCh value. Both counters have a reset value of FFFCh (this is the only value which is reloaded in the 16-bit timer). The reset value of both counters is also FFFCh in One Pulse mode and PWM mode. The timer clock depends on the clock control bits of the CR2 register, as illustrated in Table 18 Clock Control Bits. The value in the counter register repeats every 131072, 262144 or 524288 CPU clock cycles depending on the CC[1:0] bits. The timer frequency can be fCPU/2, fCPU/4, fCPU/8 or an external frequency.
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16-BIT TIMER (Cont'd) Figure 35. Timer Block Diagram
ST7 INTERNAL BUS fCPU MCU-PERIPHERAL INTERFACE
8 high
8 low
8-bit buffer
8 high low
8 high
8 low
8 high
8 low
8 high
8 low
8
EXEDG
16
1/2 1/4 1/8 EXTCLK pin COUNTER REGISTER ALTERNATE COUNTER REGISTER OUTPUT COMPARE REGISTER 1 OUTPUT COMPARE REGISTER 2 INPUT CAPTURE REGISTER 1 INPUT CAPTURE REGISTER 2
16
16
16
CC[1:0] TIMER INTERNAL BUS 16 16 OVERFLOW DETECT CIRCUIT
OUTPUT COMPARE CIRCUIT
EDGE DETECT CIRCUIT1
ICAP1 pin
6
EDGE DETECT CIRCUIT2
ICAP2 pin
LATCH1
ICF1 OCF1 TOF ICF2 OCF2 0
OCMP1 pin OCMP2 pin
0
0 LATCH2
(Status Register) SR
ICIE OCIE TOIE FOLV2 FOLV1OLVL2 IEDG1 OLVL1
OC1E OC2E OPM PWM
CC1
CC0 IEDG2 EXEDG
(Control Register 1) CR1
(Control Register 2) CR2
(See note) TIMER INTERRUPT
Note: If IC, OC and TO interrupt requests have separate vectors then the last OR is not present (See device Interrupt Vector Table)
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16-BIT TIMER (Cont'd) 16-bit Read Sequence: (from either the Counter Register or the Alternate Counter Register).
Beginning of the sequence
At t0 Read MS Byte Other instructions Read At t0 +t LS Byte
Returns the buffered
LS Byte is buffered
LS Byte value at t0
Sequence completed
The user must read the MS Byte first, then the LS Byte value is buffered automatically. This buffered value remains unchanged until the 16-bit read sequence is completed, even if the user reads the MS Byte several times. After a complete reading sequence, if only the CLR register or ACLR register are read, they return the LS Byte of the count value at the time of the read. Whatever the timer mode used (input capture, output compare, One Pulse mode or PWM mode) an overflow occurs when the counter rolls over from FFFFh to 0000h then: - The TOF bit of the SR register is set. - A timer interrupt is generated if: - TOIE bit of the CR1 register is set and - I bit of the CC register is cleared. If one of these conditions is false, the interrupt remains pending to be issued as soon as they are both true.
Clearing the overflow interrupt request is done in two steps: 1. Reading the SR register while the TOF bit is set. 2. An access (read or write) to the CLR register. Note: The TOF bit is not cleared by accessing the ACLR register. The advantage of accessing the ACLR register rather than the CLR register is that it allows simultaneous use of the overflow function and reading the free running counter at random times (for example, to measure elapsed time) without the risk of clearing the TOF bit erroneously. The timer is not affected by WAIT mode. In HALT mode, the counter stops counting until the mode is exited. Counting then resumes from the previous count (MCU awakened by an interrupt) or from the reset count (MCU awakened by a Reset). 10.4.3.2 External Clock The external clock (where available) is selected if CC0=1 and CC1=1 in the CR2 register. The status of the EXEDG bit in the CR2 register determines the type of level transition on the external clock pin EXTCLK that will trigger the free running counter. The counter is synchronised with the falling edge of the internal CPU clock. A minimum of four falling edges of the CPU clock must occur between two consecutive active edges of the external clock; thus the external clock frequency must be less than a quarter of the CPU clock frequency.
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16-BIT TIMER (Cont'd) Figure 36. Counter Timing Diagram, internal clock divided by 2
CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) FFFD FFFE FFFF 0000 0001 0002 0003
Figure 37. Counter Timing Diagram, internal clock divided by 4
CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) FFFC FFFD 0000 0001
Figure 38. Counter Timing Diagram, internal clock divided by 8
CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER FFFC FFFD 0000
TIMER OVERFLOW FLAG (TOF)
Note: The MCU is in reset state when the internal reset signal is high. When it is low, the MCU is running.
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16-BIT TIMER (Cont'd) 10.4.3.3 Input Capture In this section, the index, i, may be 1 or 2 because there are 2 input capture functions in the 16-bit timer. The two input capture 16-bit registers (IC1R and IC2R) are used to latch the value of the free running counter after a transition is detected by the ICAPi pin (see figure 5).
ICiR MS Byte ICiHR LS Byte ICiLR
The ICiR register is a read-only register. The active transition is software programmable through the IEDGi bit of Control Registers (CRi). Timing resolution is one count of the free running counter: (fCPU/CC[1:0]). Procedure: To use the input capture function, select the following in the CR2 register: - Select the timer clock (CC[1:0]) (see Table 18 Clock Control Bits). - Select the edge of the active transition on the ICAP2 pin with the IEDG2 bit (the ICAP2 pin must be configured as a floating input or input with pull-up without interrupt if this configuration is available). And select the following in the CR1 register: - Set the ICIE bit to generate an interrupt after an input capture coming from either the ICAP1 pin or the ICAP2 pin - Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the ICAP1 pin must be configured as a floating input or input with pull-up without interrupt if this configuration is available).
When an input capture occurs: - The ICFi bit is set. - The ICiR register contains the value of the free running counter on the active transition on the ICAPi pin (see Figure 40). - A timer interrupt is generated if the ICIE bit is set and the I bit is cleared in the CC register. Otherwise, the interrupt remains pending until both conditions become true. Clearing the Input Capture interrupt request (i.e. clearing the ICFi bit) is done in two steps: 1. Reading the SR register while the ICFi bit is set. 2. An access (read or write) to the ICiLR register. Notes: 1. After reading the ICiHR register, the transfer of input capture data is inhibited and ICFi will never be set until the ICiLR register is also read. 2. The ICiR register contains the free running counter value which corresponds to the most recent input capture. 3. The 2 input capture functions can be used together even if the timer also uses the 2 output compare functions. 4. In One Pulse mode and PWM mode only the input capture 2 function can be used. 5. The alternate inputs (ICAP1 & ICAP2) are always directly connected to the timer. So any transitions on these pins activate the input capture function. Moreover if one of the ICAPi pin is configured as an input and the second one as an output, an interrupt can be generated if the user toggles the output pin and if the ICIE bit is set. This can be avoided if the input capture function i is disabled by reading the ICiHR (see note 1). 6. The TOF bit can be used with an interrupt in order to measure events that exceed the timer range (FFFFh).
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16-BIT TIMER (Cont'd) Figure 39. Input Capture Block Diagram
ICAP1 pin ICAP2 pin EDGE DETECT CIRCUIT2 EDGE DETECT CIRCUIT1
ICIE
(Control Register 1) CR1
IEDG1
(Status Register) SR IC2R Register IC1R Register
ICF1 ICF2 0 0 0
16-BIT
(Control Register 2) CR2
CC1 CC0 IEDG2
16-BIT FREE RUNNING
COUNTER
Figure 40. Input Capture Timing Diagram
TIMER CLOCK COUNTER REGISTER ICAPi PIN ICAPi FLAG ICAPi REGISTER Note: Active edge is rising edge. FF03 FF01 FF02 FF03
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16-BIT TIMER (Cont'd) 10.4.3.4 Output Compare In this section, the index, i, may be 1 or 2 because there are 2 output compare functions in the 16-bit timer. This function can be used to control an output waveform or indicate when a period of time has elapsed. When a match is found between the Output Compare register and the free running counter, the output compare function: - Assigns pins with a programmable value if the OCiE bit is set - Sets a flag in the status register - Generates an interrupt if enabled Two 16-bit registers Output Compare Register 1 (OC1R) and Output Compare Register 2 (OC2R) contain the value to be compared to the counter register each timer clock cycle.
OCiR MS Byte OCiHR LS Byte OCiLR
- The OCMPi pin takes OLVLi bit value (OCMPi pin latch is forced low during reset). - A timer interrupt is generated if the OCIE bit is set in the CR1 register and the I bit is cleared in the CC register (CC). The OCiR register value required for a specific timing application can be calculated using the following formula:
OCiR =
Where:
t * fCPU
PRESC
t
fCPU
= Output compare period (in seconds) = CPU clock frequency (in hertz) PRESC = Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see Table 18 Clock Control Bits)
These registers are readable and writable and are not affected by the timer hardware. A reset event changes the OCiR value to 8000h. Timing resolution is one count of the free running counter: (fCPU/CC[1:0]). Procedure: To use the output compare function, select the following in the CR2 register: - Set the OCiE bit if an output is needed then the OCMPi pin is dedicated to the output compare i signal. - Select the timer clock (CC[1:0]) (see Table 18 Clock Control Bits). And select the following in the CR1 register: - Select the OLVLi bit to applied to the OCMPi pins after the match occurs. - Set the OCIE bit to generate an interrupt if it is needed. When a match is found between OCRi register and CR register: - OCFi bit is set.
If the timer clock is an external clock, the formula is:
OCiR = t * fEXT
Where:
t
fEXT
= Output compare period (in seconds) = External timer clock frequency (in hertz)
Clearing the output compare interrupt request (i.e. clearing the OCFi bit) is done by: 1. Reading the SR register while the OCFi bit is set. 2. An access (read or write) to the OCiLR register. The following procedure is recommended to prevent the OCFi bit from being set between the time it is read and the write to the OCiR register: - Write to the OCiHR register (further compares are inhibited). - Read the SR register (first step of the clearance of the OCFi bit, which may be already set). - Write to the OCiLR register (enables the output compare function and clears the OCFi bit).
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16-BIT TIMER (Cont'd) Notes: 1. After a processor write cycle to the OCiHR register, the output compare function is inhibited until the OCiLR register is also written. 2. If the OCiE bit is not set, the OCMPi pin is a general I/O port and the OLVLi bit will not appear when a match is found but an interrupt could be generated if the OCIE bit is set. 3. When the timer clock is fCPU/2, OCFi and OCMPi are set while the counter value equals the OCiR register value (see Figure 42 on page 69). This behaviour is the same in OPM or PWM mode. When the timer clock is fCPU/4, fCPU/8 or in external clock mode, OCFi and OCMPi are set while the counter value equals the OCiR register value plus 1 (see Figure 43 on page 69). 4. The output compare functions can be used both for generating external events on the OCMPi pins even if the input capture mode is also used. 5. The value in the 16-bit OCiR register and the OLVi bit should be changed after each successful comparison in order to control an output waveform or establish a new elapsed timeout. Figure 41. Output Compare Block Diagram
Forced Compare Output capability When the FOLVi bit is set by software, the OLVLi bit is copied to the OCMPi pin. The OLVi bit has to be toggled in order to toggle the OCMPi pin when it is enabled (OCiE bit=1). The OCFi bit is then not set by hardware, and thus no interrupt request is generated. FOLVLi bits have no effect in either One-Pulse mode or PWM mode.
16 BIT FREE RUNNING COUNTER
OC1E OC2E
CC1
CC0
16-bit
OUTPUT COMPARE CIRCUIT
(Control Register 2) CR2 (Control Register 1) CR1
OCIE FOLV2 FOLV1 OLVL2 OLVL1 Latch 1
OCMP1 Pin OCMP2 Pin
16-bit
16-bit
OC1R Register
OCF1 OCF2 0 0 0
Latch 2
OC2R Register (Status Register) SR
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16-BIT TIMER (Cont'd) Figure 42. Output Compare Timing Diagram, fTIMER =fCPU/2
INTERNAL CPU CLOCK TIMER CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER i (OCRi) OUTPUT COMPARE FLAG i (OCFi) OCMPi PIN (OLVLi=1) 2ECF 2ED0 2ED1 2ED2 2ED3 2ED4 2ED3
Figure 43. Output Compare Timing Diagram, fTIMER =fCPU/4
INTERNAL CPU CLOCK TIMER CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER i (OCRi) COMPARE REGISTER i LATCH OUTPUT COMPARE FLAG i (OCFi) OCMPi PIN (OLVLi=1) 2ECF 2ED0 2ED1 2ED2 2ED3 2ED4 2ED3
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16-BIT TIMER (Cont'd) 10.4.3.5 One Pulse Mode One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register. The One Pulse mode uses the Input Capture1 function and the Output Compare1 function. Procedure: To use One Pulse mode: 1. Load the OC1R register with the value corresponding to the length of the pulse (see the formula in the opposite column). 2. Select the following in the CR1 register: - Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after the pulse. - Using the OLVL2 bit, select the level to be applied to the OCMP1 pin during the pulse. - Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the ICAP1 pin must be configured as floating input). 3. Select the following in the CR2 register: - Set the OC1E bit, the OCMP1 pin is then dedicated to the Output Compare 1 function. - Set the OPM bit. - Select the timer clock CC[1:0] (see Table 18 Clock Control Bits).
Clearing the Input Capture interrupt request (i.e. clearing the ICFi bit) is done in two steps: 1. Reading the SR register while the ICFi bit is set. 2. An access (read or write) to the ICiLR register. The OC1R register value required for a specific timing application can be calculated using the following formula: OCiR Value =
t * fCPU
PRESC
-5
Where: t = Pulse period (in seconds) fCPU = CPU clock frequency (in hertz) PRESC = Timer prescaler factor (2, 4 or 8 depending on the CC[1:0] bits, see Table 18 Clock Control Bits) If the timer clock is an external clock the formula is: OCiR = t * fEXT -5 Where: t = Pulse period (in seconds) fEXT = External timer clock frequency (in hertz) When the value of the counter is equal to the value of the contents of the OC1R register, the OLVL1 bit is output on the OCMP1 pin (see Figure 44). Notes: 1. The OCF1 bit cannot be set by hardware in One Pulse mode but the OCF2 bit can generate an Output Compare interrupt. 2. When the Pulse Width Modulation (PWM) and One Pulse mode (OPM) bits are both set, the PWM mode is the only active one. 3. If OLVL1=OLVL2 a continuous signal will be seen on the OCMP1 pin. 4. The ICAP1 pin can not be used to perform input capture. The ICAP2 pin can be used to perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset each time a valid edge occurs on the ICAP1 pin and ICF1 can also generates interrupt if ICIE is set. 5. When One Pulse mode is used OC1R is dedicated to this mode. Nevertheless OC2R and OCF2 can be used to indicate that a period of time has elapsed but cannot generate an output waveform because the OLVL2 level is dedicated to One Pulse mode.
One Pulse mode cycle
When event occurs on ICAP1 OCMP1 = OLVL2 Counter is reset to FFFCh ICF1 bit is set When Counter = OC1R
OCMP1 = OLVL1
Then, on a valid event on the ICAP1 pin, the counter is initialized to FFFCh and the OLVL2 bit is loaded on the OCMP1 pin, the ICF1 bit is set and the value FFFDh is loaded in the IC1R register. Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the ICIE bit is set.
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16-BIT TIMER (Cont'd) Figure 44. One Pulse Mode Timing Example
COUNTER ICAP1 OCMP1
FFFC FFFD FFFE
2ED0 2ED1 2ED2 2ED3
FFFC FFFD
OLVL2
OLVL1
OLVL2
compare1 Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1
Figure 45. Pulse Width Modulation Mode Timing Example
COUNTER 34E2 FFFC FFFD FFFE OCMP1
2ED0 2ED1 2ED2
34E2
FFFC
OLVL2
OLVL1
OLVL2
compare2
compare1
compare2
Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1
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16-BIT TIMER (Cont'd) 10.4.3.6 Pulse Width Modulation Mode Pulse Width Modulation (PWM) mode enables the generation of a signal with a frequency and pulse length determined by the value of the OC1R and OC2R registers. The Pulse Width Modulation mode uses the complete Output Compare 1 function plus the OC2R register, and so these functions cannot be used when the PWM mode is activated. Procedure To use Pulse Width Modulation mode: 1. Load the OC2R register with the value corresponding to the period of the signal using the formula in the opposite column. 2. Load the OC1R register with the value corresponding to the period of the pulse if OLVL1=0 and OLVL2=1, using the formula in the opposite column. 3. Select the following in the CR1 register: - Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after a successful comparison with OC1R register. - Using the OLVL2 bit, select the level to be applied to the OCMP1 pin after a successful comparison with OC2R register. 4. Select the following in the CR2 register: - Set OC1E bit: the OCMP1 pin is then dedicated to the output compare 1 function. - Set the PWM bit. - Select the timer clock (CC[1:0]) (see Table 18 Clock Control Bits). If OLVL1=1 and OLVL2=0, the length of the positive pulse is the difference between the OC2R and OC1R registers. If OLVL1=OLVL2 a continuous signal will be seen on the OCMP1 pin.
The OCiR register value required for a specific timing application can be calculated using the following formula: OCiR Value =
t * fCPU
PRESC
-5
Where: t = Signal or pulse period (in seconds) fCPU = CPU clock frequency (in hertz) PRESC = Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see Table 18 Clock Control Bits) If the timer clock is an external clock the formula is: OCiR = t * fEXT -5 Where: t = Signal or pulse period (in seconds) fEXT = External timer clock frequency (in hertz) The Output Compare 2 event causes the counter to be initialized to FFFCh (See Figure 45) Notes: 1. After a write instruction to the OCiHR register, the output compare function is inhibited until the OCiLR register is also written. 2. The OCF1 and OCF2 bits cannot be set by hardware in PWM mode, therefore the Output Compare interrupt is inhibited. 3. The ICF1 bit is set by hardware when the counter reaches the OC2R value and can produce a timer interrupt if the ICIE bit is set and the I bit is cleared. 4. In PWM mode the ICAP1 pin can not be used to perform input capture because it is disconnected from the timer. The ICAP2 pin can be used to perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset after each period and ICF1 can also generate an interrupt if ICIE is set. 5. When the Pulse Width Modulation (PWM) and One Pulse mode (OPM) bits are both set, the PWM mode is the only active one.
Pulse Width Modulation cycle
When Counter = OC1R
OCMP1 = OLVL1
When Counter = OC2R
OCMP1 = OLVL2 Counter is reset to FFFCh ICF1 bit is set
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16-BIT TIMER (Cont'd) 10.4.4 Low Power Modes
Mode WAIT Description No effect on 16-bit Timer. Timer interrupts cause the device to exit from WAIT mode. 16-bit Timer registers are frozen. In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous count when the MCU is woken up by an interrupt with "exit from HALT mode" capability or from the counter reset value when the MCU is woken up by a RESET. If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequently, when the MCU is woken up by an interrupt with "exit from HALT mode" capability, the ICFi bit is set, and the counter value present when exiting from HALT mode is captured into the ICiR register.
HALT
10.4.5 Interrupts
Interrupt Event Input Capture 1 event/Counter reset in PWM mode Input Capture 2 event Output Compare 1 event (not available in PWM mode) Output Compare 2 event (not available in PWM mode) Timer Overflow event Event Flag ICF1 ICF2 OCF1 OCF2 TOF Enable Control Bit ICIE OCIE TOIE Exit from Wait Yes Yes Yes Yes Yes Exit from Halt No No No No No
Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chapter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction). 10.4.6 Summary of Timer modes
MODES Input Capture (1 and/or 2) Output Compare (1 and/or 2) One Pulse mode PWM Mode
1) 2)
Input Capture 1 Yes Yes No No
AVAILABLE RESOURCES Input Capture 2 Output Compare 1 Output Compare 2 Yes Yes Yes Yes Yes Yes No Partially 2) Not Recommended1) Not Recommended3) No No
See note 4 in Section 10.4.3.5 "One Pulse Mode" on page 70 See note 5 in Section 10.4.3.5 "One Pulse Mode" on page 70 3) See note 4 in Section 10.4.3.6 "Pulse Width Modulation Mode" on page 72
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16-BIT TIMER (Cont'd) 10.4.7 Register Description Each Timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the alternate counter. CONTROL REGISTER 1 (CR1) Read/Write Reset Value: 0000 0000 (00h)
7 0
Bit 4 = FOLV2 Forced Output Compare 2. This bit is set and cleared by software. 0: No effect on the OCMP2 pin. 1: Forces the OLVL2 bit to be copied to the OCMP2 pin, if the OC2E bit is set and even if there is no successful comparison. Bit 3 = FOLV1 Forced Output Compare 1. This bit is set and cleared by software. 0: No effect on the OCMP1 pin. 1: Forces OLVL1 to be copied to the OCMP1 pin, if the OC1E bit is set and even if there is no successful comparison. Bit 2 = OLVL2 Output Level 2. This bit is copied to the OCMP2 pin whenever a successful comparison occurs with the OC2R register and OCxE is set in the CR2 register. This value is copied to the OCMP1 pin in One Pulse mode and Pulse Width Modulation mode. Bit 1 = IEDG1 Input Edge 1. This bit determines which type of level transition on the ICAP1 pin will trigger the capture. 0: A falling edge triggers the capture. 1: A rising edge triggers the capture. Bit 0 = OLVL1 Output Level 1. The OLVL1 bit is copied to the OCMP1 pin whenever a successful comparison occurs with the OC1R register and the OC1E bit is set in the CR2 register.
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
Bit 7 = ICIE Input Capture Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is generated whenever the ICF1 or ICF2 bit of the SR register is set. Bit 6 = OCIE Output Compare Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is generated whenever the OCF1 or OCF2 bit of the SR register is set. Bit 5 = TOIE Timer Overflow Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is enabled whenever the TOF bit of the SR register is set.
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16-BIT TIMER (Cont'd) CONTROL REGISTER 2 (CR2) Read/Write Reset Value: 0000 0000 (00h)
7 0
OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG
Bit 4 = PWM Pulse Width Modulation. 0: PWM mode is not active. 1: PWM mode is active, the OCMP1 pin outputs a programmable cyclic signal; the length of the pulse depends on the value of OC1R register; the period depends on the value of OC2R register. Bits 3:2 = CC[1:0] Clock Control. The timer clock mode depends on these bits: Table 18. Clock Control Bits
Timer Clock fCPU / 4 fCPU / 2 fCPU / 8 External Clock (where available) CC1 0 0 1 1 CC0 0 1 0 1
Bit 7 = OC1E Output Compare 1 Pin Enable. This bit is used only to output the signal from the timer on the OCMP1 pin (OLV1 in Output Compare mode, both OLV1 and OLV2 in PWM and one-pulse mode). Whatever the value of the OC1E bit, the internal Output Compare 1 function of the timer remains active. 0: OCMP1 pin alternate function disabled (I/O pin free for general-purpose I/O). 1: OCMP1 pin alternate function enabled. Bit 6 = OC2E Output Compare 2 Pin Enable. This bit is used only to output the signal from the timer on the OCMP2 pin (OLV2 in Output Compare mode). Whatever the value of the OC2E bit, the internal Output Compare 2 function of the timer remains active. 0: OCMP2 pin alternate function disabled (I/O pin free for general-purpose I/O). 1: OCMP2 pin alternate function enabled. Bit 5 = OPM One Pulse mode. 0: One Pulse mode is not active. 1: One Pulse mode is active, the ICAP1 pin can be used to trigger one pulse on the OCMP1 pin; the active transition is given by the IEDG1 bit. The length of the generated pulse depends on the contents of the OC1R register.
Note: If the external clock pin is not available, programming the external clock configuration stops the counter. Bit 1 = IEDG2 Input Edge 2. This bit determines which type of level transition on the ICAP2 pin will trigger the capture. 0: A falling edge triggers the capture. 1: A rising edge triggers the capture. Bit 0 = EXEDG External Clock Edge. This bit determines which type of level transition on the external clock pin (EXTCLK) will trigger the counter register. 0: A falling edge triggers the counter register. 1: A rising edge triggers the counter register.
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16-BIT TIMER (Cont'd) STATUS REGISTER (SR) Read Only Reset Value: 0000 0000 (00h) The three least significant bits are not used.
7 ICF1 OCF1 TOF ICF2 OCF2 0 0 0 0
INPUT CAPTURE 1 HIGH REGISTER (IC1HR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event).
7 MSB 0 LSB
Bit 7 = ICF1 Input Capture Flag 1. 0: No input capture (reset value). 1: An input capture has occurred on the ICAP1 pin or the counter has reached the OC2R value in PWM mode. To clear this bit, first read the SR register, then read or write the low byte of the IC1R (IC1LR) register. Bit 6 = OCF1 Output Compare Flag 1. 0: No match (reset value). 1: The content of the free running counter matches the content of the OC1R register. To clear this bit, first read the SR register, then read or write the low byte of the OC1R (OC1LR) register. Bit 5 = TOF Timer Overflow Flag. 0: No timer overflow (reset value). 1: The free running counter has rolled over from FFFFh to 0000h. To clear this bit, first read the SR register, then read or write the low byte of the CR (CLR) register. Note: Reading or writing the ACLR register does not clear TOF. Bit 4 = ICF2 Input Capture Flag 2. 0: No input capture (reset value). 1: An input capture has occurred on the ICAP2 pin. To clear this bit, first read the SR register, then read or write the low byte of the IC2R (IC2LR) register. Bit 3 = OCF2 Output Compare Flag 2. 0: No match (reset value). 1: The content of the free running counter matches the content of the OC2R register. To clear this bit, first read the SR register, then read or write the low byte of the OC2R (OC2LR) register. Bit 2-0 = Reserved, forced by hardware to 0.
INPUT CAPTURE 1 LOW REGISTER (IC1LR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the low part of the counter value (transferred by the input capture 1 event).
7 MSB 0 LSB
OUTPUT COMPARE 1 HIGH REGISTER (OC1HR) Read/Write Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register.
7 MSB 0 LSB
OUTPUT COMPARE 1 LOW REGISTER (OC1LR) Read/Write Reset Value: 0000 0000 (00h) This is an 8-bit register that contains the low part of the value to be compared to the CLR register.
7 MSB 0 LSB
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16-BIT TIMER (Cont'd) OUTPUT COMPARE 2 HIGH REGISTER (OC2HR) Read/Write Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register.
7 MSB 0 LSB
ALTERNATE COUNTER HIGH REGISTER (ACHR) Read Only Reset Value: 1111 1111 (FFh) This is an 8-bit register that contains the high part of the counter value.
7 MSB 0 LSB
OUTPUT COMPARE 2 LOW REGISTER (OC2LR) Read/Write Reset Value: 0000 0000 (00h) This is an 8-bit register that contains the low part of the value to be compared to the CLR register.
7 MSB 0 LSB
ALTERNATE COUNTER LOW REGISTER (ACLR) Read Only Reset Value: 1111 1100 (FCh) This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after an access to SR register does not clear the TOF bit in SR register.
7 0 LSB
COUNTER HIGH REGISTER (CHR) Read Only Reset Value: 1111 1111 (FFh) This is an 8-bit register that contains the high part of the counter value.
7 MSB 0 LSB
MSB
INPUT CAPTURE 2 HIGH REGISTER (IC2HR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the high part of the counter value (transferred by the Input Capture 2 event).
7 0 LSB
COUNTER LOW REGISTER (CLR) Read Only Reset Value: 1111 1100 (FCh) This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after accessing the SR register clears the TOF bit.
7 MSB 0 LSB
MSB
INPUT CAPTURE 2 LOW REGISTER (IC2LR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the low part of the counter value (transferred by the Input Capture 2 event).
7 MSB 0 LSB
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16-BIT TIMER (Cont'd) Table 19. 16-Bit Timer Register Map and Reset Values
Address (Hex.) Register Label 7 ICIE 0 OC1E 0 ICF1 0 MSB MSB MSB MSB MSB MSB MSB 1 MSB 1 MSB 1 MSB 1 MSB MSB 6 OCIE 0 OC2E 0 OCF1 0 5 TOIE 0 OPM 0 TOF 0 4 FOLV2 0 PWM 0 ICF2 0 3 FOLV1 0 CC1 0 OCF2 0 2 OLVL2 0 CC0 0 0 1 IEDG1 0 IEDG2 0 0 0 OLVL1 0 EXEDG 0 0 LSB LSB LSB LSB LSB LSB LSB 1 LSB 0 LSB 1 LSB 0 LSB LSB -
Timer A: 32 CR1 Timer B: 42 Reset Value Timer A: 31 CR2 Timer B: 41 Reset Value Timer A: 33 SR Timer B: 43 Reset Value Timer A: 34 ICHR1 Timer B: 44 Reset Value Timer A: 35 ICLR1 Timer B: 45 Reset Value Timer A: 36 OCHR1 Timer B: 46 Reset Value Timer A: 37 OCLR1 Timer B: 47 Reset Value Timer A: 3E OCHR2 Timer B: 4E Reset Value Timer A: 3F OCLR2 Timer B: 4F Reset Value Timer A: 38 CHR Timer B: 48 Reset Value Timer A: 39 CLR Timer B: 49 Reset Value Timer A: 3A ACHR Timer B: 4A Reset Value Timer A: 3B ACLR Timer B: 4B Reset Value Timer A: 3C ICHR2 Timer B: 4C Reset Value Timer A: 3D ICLR2 Timer B: 4D Reset Value
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1 -
1 -
1 -
1 -
1 -
0 -
-
-
-
-
-
-
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10.5 SERIAL PERIPHERAL INTERFACE (SPI) 10.5.1 Introduction The Serial Peripheral Interface (SPI) allows fullduplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves or a system in which devices may be either masters or slaves. The SPI is normally used for communication between the microcontroller and external peripherals or another microcontroller. Refer to the Pin Description chapter for the devicespecific pin-out. 10.5.2 Main Features s Full duplex, three-wire synchronous transfers s Master or slave operation s Four master mode frequencies s Maximum slave mode frequency = fCPU/4. s Four programmable master bit rates s Programmable clock polarity and phase s End of transfer interrupt flag s Write collision flag protection s Master mode fault protection capability. 10.5.3 General description The SPI is connected to external devices through 4 alternate pins: - MISO: Master In Slave Out pin - MOSI: Master Out Slave In pin - SCK: Serial Clock pin - SS: Slave select pin A basic example of interconnections between a single master and a single slave is illustrated on Figure 46. The MOSI pins are connected together as are MISO pins. In this way data is transferred serially between master and slave (most significant bit first). When the master device transmits data to a slave device via MOSI pin, the slave device responds by sending data to the master device via the MISO pin. This implies full duplex transmission with both data out and data in synchronized with the same clock signal (which is provided by the master device via the SCK pin). Thus, the byte transmitted is replaced by the byte received and eliminates the need for separate transmit-empty and receiver-full bits. A status flag is used to indicate that the I/O operation is complete. Four possible data/clock timing relationships may be chosen (see Figure 49) but master and slave must be programmed with the same timing mode.
Figure 46. Serial Peripheral Interface Master/Slave
MASTER MSBit LSBit MISO MISO MSBit SLAVE LSBit
8-BIT SHIFT REGISTER
8-BIT SHIFT REGISTER
MOSI
MOSI
SPI CLOCK GENERATOR
SCK
SCK +5V
SS
SS
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SERIAL PERIPHERAL INTERFACE (Cont'd) Figure 47. Serial Peripheral Interface Block Diagram
Internal Bus Read Read Buffer
DR IT request
MOSI MISO
8-Bit Shift Register
SPIF WCOL - MODF -
SR
-
Write SPI STATE CONTROL
SCK SS
CR
SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
MASTER CONTROL
SERIAL CLOCK GENERATOR
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SERIAL PERIPHERAL INTERFACE (Cont'd) 10.5.4 Functional Description Figure 46 shows the serial peripheral interface (SPI) block diagram. This interface contains 3 dedicated registers: - A Control Register (CR) - A Status Register (SR) - A Data Register (DR) Refer to the CR, SR and DR registers in Section 10.5.7for the bit definitions. 10.5.4.1 Master Configuration In a master configuration, the serial clock is generated on the SCK pin. Procedure - Select the SPR0 & SPR1 bits to define the serial clock baud rate (see CR register). - Select the CPOL and CPHA bits to define one of the four relationships between the data transfer and the serial clock (see Figure 49). - The SS pin must be connected to a high level signal during the complete byte transmit sequence. - The MSTR and SPE bits must be set (they remain set only if the SS pin is connected to a high level signal).
In this configuration the MOSI pin is a data output and to the MISO pin is a data input. Transmit sequence The transmit sequence begins when a byte is written the DR register. The data byte is parallel loaded into the 8-bit shift register (from the internal bus) during a write cycle and then shifted out serially to the MOSI pin most significant bit first. When data transfer is complete: - The SPIF bit is set by hardware - An interrupt is generated if the SPIE bit is set and the I bit in the CCR register is cleared. During the last clock cycle the SPIF bit is set, a copy of the data byte received in the shift register is moved to a buffer. When the DR register is read, the SPI peripheral returns this buffered value. Clearing the SPIF bit is performed by the following software sequence: 1. An access to the SR register while the SPIF bit is set 2. A read to the DR register. Note: While the SPIF bit is set, all writes to the DR register are inhibited until the SR register is read.
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SERIAL PERIPHERAL INTERFACE (Cont'd) 10.5.4.2 Slave Configuration In slave configuration, the serial clock is received on the SCK pin from the master device. The value of the SPR0 & SPR1 bits is not used for the data transfer. Procedure - For correct data transfer, the slave device must be in the same timing mode as the master device (CPOL and CPHA bits). See Figure 49. - The SS pin must be connected to a low level signal during the complete byte transmit sequence. - Clear the MSTR bit and set the SPE bit to assign the pins to alternate function. In this configuration the MOSI pin is a data input and the MISO pin is a data output. Transmit Sequence The data byte is parallel loaded into the 8-bit shift register (from the internal bus) during a write cycle and then shifted out serially to the MISO pin most significant bit first. The transmit sequence begins when the slave device receives the clock signal and the most significant bit of the data on its MOSI pin.
When data transfer is complete: - The SPIF bit is set by hardware - An interrupt is generated if SPIE bit is set and I bit in CCR register is cleared. During the last clock cycle the SPIF bit is set, a copy of the data byte received in the shift register is moved to a buffer. When the DR register is read, the SPI peripheral returns this buffered value. Clearing the SPIF bit is performed by the following software sequence: 1. An access to the SR register while the SPIF bit is set. 2.A read to the DR register. Notes: While the SPIF bit is set, all writes to the DR register are inhibited until the SR register is read. The SPIF bit can be cleared during a second transmission; however, it must be cleared before the second SPIF bit in order to prevent an overrun condition (see Section 10.5.4.6). Depending on the CPHA bit, the SS pin has to be set to write to the DR register between each data byte transfer to avoid a write collision (see Section 10.5.4.4).
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SERIAL PERIPHERAL INTERFACE (Cont'd) 10.5.4.3 Data Transfer Format During an SPI transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). The serial clock is used to synchronize the data transfer during a sequence of eight clock pulses. The SS pin allows individual selection of a slave device; the other slave devices that are not selected do not interfere with the SPI transfer. Clock Phase and Clock Polarity Four possible timing relationships may be chosen by software, using the CPOL and CPHA bits. The CPOL (clock polarity) bit controls the steady state value of the clock when no data is being transferred. This bit affects both master and slave modes. The combination between the CPOL and CPHA (clock phase) bits selects the data capture clock edge. Figure 49, shows an SPI transfer with the four combinations of the CPHA and CPOL bits. The diagram may be interpreted as a master or slave timing diagram where the SCK pin, the MISO pin, the MOSI pin are directly connected between the master and the slave device. The SS pin is the slave device select input and can be driven by the master device.
The master device applies data to its MOSI pinclock edge before the capture clock edge. CPHA bit is set The second edge on the SCK pin (falling edge if the CPOL bit is reset, rising edge if the CPOL bit is set) is the MSBit capture strobe. Data is latched on the occurrence of the second clock transition. No write collision should occur even if the SS pin stays low during a transfer of several bytes (see Figure 48). CPHA bit is reset The first edge on the SCK pin (falling edge if CPOL bit is set, rising edge if CPOL bit is reset) is the MSBit capture strobe. Data is latched on the occurrence of the first clock transition. The SS pin must be toggled high and low between each byte transmitted (see Figure 48). To protect the transmission from a write collision a low value on the SS pin of a slave device freezes the data in its DR register and does not allow it to be altered. Therefore the SS pin must be high to write a new data byte in the DR without producing a write collision.
Figure 48. CPHA / SS Timing Diagram
MOSI/MISO Master SS Slave SS (CPHA=0) Slave SS (CPHA=1)
Byte 1
Byte 2
Byte 3
VR02131A
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SERIAL PERIPHERAL INTERFACE (Cont'd) Figure 49. Data Clock Timing Diagram
CPHA =1
SCLK (with CPOL = 1) SCLK (with CPOL = 0)
MISO (from master) MOSI (from slave) SS (to slave)
CAPTURE STROBE
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
CPHA =0
CPOL = 1
CPOL = 0
MISO (from master) MOSI (from slave) SS (to slave)
CAPTURE STROBE
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
Note: This figure should not be used as a replacement for parametric information. Refer to the Electrical Characteristics chapter.
VR02131B
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SERIAL PERIPHERAL INTERFACE (Cont'd) 10.5.4.4 Write Collision Error A write collision occurs when the software tries to write to the DR register while a data transfer is taking place with an external device. When this happens, the transfer continues uninterrupted; and the software write will be unsuccessful. Write collisions can occur both in master and slave mode. Note: a "read collision" will never occur since the received data byte is placed in a buffer in which access is always synchronous with the MCU operation. In Slave mode When the CPHA bit is set: The slave device will receive a clock (SCK) edge prior to the latch of the first data transfer. This first clock edge will freeze the data in the slave device DR register and output the MSBit on to the external MISO pin of the slave device. The SS pin low state enables the slave device but the output of the MSBit onto the MISO pin does not take place until the first data transfer clock edge.
When the CPHA bit is reset: Data is latched on the occurrence of the first clock transition. The slave device does not have any way of knowing when that transition will occur; therefore, the slave device collision occurs when software attempts to write the DR register after its SS pin has been pulled low. For this reason, the SS pin must be high, between each data byte transfer, to allow the CPU to write in the DR register without generating a write collision. In Master mode Collision in the master device is defined as a write of the DR register while the internal serial clock (SCK) is in the process of transfer. The SS pin signal must be always high on the master device. WCOL bit The WCOL bit in the SR register is set if a write collision occurs. No SPI interrupt is generated when the WCOL bit is set (the WCOL bit is a status flag only). Clearing the WCOL bit is done through a software sequence (see Figure 50).
Figure 50. Clearing the WCOL bit (Write Collision Flag) Software Sequence Clearing sequence after SPIF = 1 (end of a data byte transfer) 1st Step Read SR OR
THEN
Read SR
THEN
2nd Step
Read DR
SPIF =0 WCOL=0
Write DR
SPIF =0 WCOL=0 if no transfer has started WCOL=1 if a transfer has started
before the 2nd step
Clearing sequence before SPIF = 1 (during a data byte transfer) 1st Step Read SR
THEN
2nd Step
Read DR
WCOL=0
Note: Writing to the DR register instead of reading in it does not reset the WCOL bit
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SERIAL PERIPHERAL INTERFACE (Cont'd) 10.5.4.5 Master Mode Fault Master mode fault occurs when the master device has its SS pin pulled low, then the MODF bit is set. Master mode fault affects the SPI peripheral in the following ways: - The MODF bit is set and an SPI interrupt is generated if the SPIE bit is set. - The SPE bit is reset. This blocks all output from the device and disables the SPI peripheral. - The MSTR bit is reset, thus forcing the device into slave mode. Clearing the MODF bit is done through a software sequence: 1. A read or write access to the SR register while the MODF bit is set. 2. A write to the CR register. Notes: To avoid any multiple slave conflicts in the case of a system comprising several MCUs, the SS pin must be pulled high during the clearing sequence of the MODF bit. The SPE and MSTR bits
may be restored to their original state during or after this clearing sequence. Hardware does not allow the user to set the SPE and MSTR bits while the MODF bit is set except in the MODF bit clearing sequence. In a slave device the MODF bit can not be set, but in a multi master configuration the device can be in slave mode with this MODF bit set. The MODF bit indicates that there might have been a multi-master conflict for system control and allows a proper exit from system operation to a reset or default system state using an interrupt routine. 10.5.4.6 Overrun Condition An overrun condition occurs when the master device has sent several data bytes and the slave device has not cleared the SPIF bit issuing from the previous data byte transmitted. In this case, the receiver buffer contains the byte sent after the SPIF bit was last cleared. A read to the DR register returns this byte. All other bytes are lost. This condition is not detected by the SPI peripheral.
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SERIAL PERIPHERAL INTERFACE (Cont'd) 10.5.4.7 Single Master and Multimaster Configurations For more security, the slave device may respond There are two types of SPI systems: to the master with the received data byte. Then the - Single Master System master will receive the previous byte back from the - Multimaster System slave device if all MISO and MOSI pins are connected and the slave has not written its DR register. Single Master System Other transmission security methods can use A typical single master system may be configured, ports for handshake lines or data bytes with comusing an MCU as the master and four MCUs as mand fields. slaves (see Figure 51). Multi-master System The master device selects the individual slave deA multi-master system may also be configured by vices by using four pins of a parallel port to control the user. Transfer of master control could be imthe four SS pins of the slave devices. plemented using a handshake method through the The SS pins are pulled high during reset since the I/O ports or by an exchange of code messages master device ports will be forced to be inputs at through the serial peripheral interface system. that time, thus disabling the slave devices. The multi-master system is principally handled by the MSTR bit in the CR register and the MODF bit Note: To prevent a bus conflict on the MISO line in the SR register. the master allows only one active slave device during a transmission. Figure 51. Single Master Configuration
SS SCK Slave MCU MOSI MISO SCK Slave MCU
SS SCK Slave MCU
SS SCK Slave MCU
SS
MOSI MISO
MOSI MISO
MOSI MISO
MOSI MISO SCK Master MCU 5V SS Ports
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SERIAL PERIPHERAL INTERFACE (Cont'd) 10.5.5 Low Power Modes
Mode WAIT HALT Description No effect on SPI. SPI interrupt events cause the device to exit from WAIT mode. SPI registers are frozen. In HALT mode, the SPI is inactive. SPI operation resumes when the MCU is woken up by an interrupt with "exit from HALT mode" capability.
10.5.6 Interrupts
Interrupt Event SPI End of Transfer Event Master Mode Fault Event Event Flag SPIF MODF Enable Control Bit SPIE Exit from Wait Yes Yes Exit from Halt No No
Note: The SPI interrupt events are connected to the same interrupt vector (see Interrupts chapter). They generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction).
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SERIAL PERIPHERAL INTERFACE (Cont'd) 10.5.7 Register Description CONTROL REGISTER (CR) Read/Write Reset Value: 0000xxxx (0xh)
7
SPIE SPE SPR2 MSTR CPOL CPHA SPR1
0
SPR0
Bit 3 = CPOL Clock polarity. This bit is set and cleared by software. This bit determines the steady state of the serial Clock. The CPOL bit affects both the master and slave modes. 0: The steady state is a low value at the SCK pin. 1: The steady state is a high value at the SCK pin. Bit 2 = CPHA Clock phase. This bit is set and cleared by software. 0: The first clock transition is the first data capture edge. 1: The second clock transition is the first capture edge. Bit 1:0 = SPR[1:0] Serial peripheral rate. These bits are set and cleared by software.Used with the SPR2 bit, they select one of six baud rates to be used as the serial clock when the device is a master. These 2 bits have no effect in slave mode. Table 20. Serial Peripheral Baud Rate
Bit 7 = SPIE Serial peripheral interrupt enable. This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SPI interrupt is generated whenever SPIF=1 or MODF=1 in the SR register Bit 6 = SPE Serial peripheral output enable. This bit is set and cleared by software. It is also cleared by hardware when, in master mode, SS=0 (see Section 10.5.4.5 "Master Mode Fault" on page 86). 0: I/O port connected to pins 1: SPI alternate functions connected to pins The SPE bit is cleared by reset, so the SPI peripheral is not initially connected to the external pins. Bit 5 = SPR2 Divider Enable. this bit is set and cleared by software and it is cleared by reset. It is used with the SPR[1:0] bits to set the baud rate. Refer to Table 20. 0: Divider by 2 enabled 1: Divider by 2 disabled Bit 4 = MSTR Master. This bit is set and cleared by software. It is also cleared by hardware when, in master mode, SS=0 (see Section 10.5.4.5 "Master Mode Fault" on page 86). 0: Slave mode is selected 1: Master mode is selected, the function of the SCK pin changes from an input to an output and the functions of the MISO and MOSI pins are reversed.
Serial Clock fCPU/4 fCPU/8 fCPU/16 fCPU/32 fCPU/64 fCPU/128
SPR2 1 0 0 1 0 0
SPR1 0 0 0 1 1 1
SPR0 0 0 1 0 0 1
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SERIAL PERIPHERAL INTERFACE (Cont'd) STATUS REGISTER (SR) Read Only Reset Value: 0000 0000 (00h)
7 SPIF WCOL MODF 0 -
DATA I/O REGISTER (DR) Read/Write Reset Value: Undefined
7 D7 D6 D5 D4 D3 D2 D1 0 D0
Bit 7 = SPIF Serial Peripheral data transfer flag. This bit is set by hardware when a transfer has been completed. An interrupt is generated if SPIE=1 in the CR register. It is cleared by a software sequence (an access to the SR register followed by a read or write to the DR register). 0: Data transfer is in progress or has been approved by a clearing sequence. 1: Data transfer between the device and an external device has been completed. Note: While the SPIF bit is set, all writes to the DR register are inhibited. Bit 6 = WCOL Write Collision status. This bit is set by hardware when a write to the DR register is done during a transmit sequence. It is cleared by a software sequence (see Figure 50). 0: No write collision occurred 1: A write collision has been detected Bit 5 = Unused. Bit 4 = MODF Mode Fault flag. This bit is set by hardware when the SS pin is pulled low in master mode (see Section 10.5.4.5 "Master Mode Fault" on page 86). An SPI interrupt can be generated if SPIE=1 in the CR register. This bit is cleared by a software sequence (An access to the SR register while MODF=1 followed by a write to the CR register). 0: No master mode fault detected 1: A fault in master mode has been detected Bits 3-0 = Unused.
The DR register is used to transmit and receive data on the serial bus. In the master device only a write to this register will initiate transmission/reception of another byte. Notes: During the last clock cycle the SPIF bit is set, a copy of the received data byte in the shift register is moved to a buffer. When the user reads the serial peripheral data I/O register, the buffer is actually being read. Warning: A write to the DR register places data directly into the shift register for transmission. A read to the the DR register returns the value located in the buffer and not the contents of the shift register (See Figure 47 ).
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SERIAL PERIPHERAL INTERFACE (Cont'd) Table 21. SPI Register Map and Reset Values
Address (Hex.) 0021h 0022h 0023h Register Label SPIDR Reset Value SPICR Reset Value SPISR Reset Value 7 MSB x SPIE 0 SPIF 0 6 5 4 3 2 1 0 LSB x SPR0 x 0
x SPE 0 WCOL 0
x SPR2 0 0
x MSTR 0 MODF 0
x CPOL x 0
x CPHA x 0
x SPR1 x 0
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10.6 SERIAL COMMUNICATIONS INTERFACE (SCI) 10.6.1 Introduction The Serial Communications Interface (SCI) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The SCI offers a very wide range of baud rates using two baud rate generator systems. 10.6.2 Main Features s Full duplex, asynchronous communications s NRZ standard format (Mark/Space) s Dual baud rate generator systems s Independently programmable transmit and receive baud rates up to 250K baud using conventional baud rate generator and up to 500K baud using the extended baud rate generator. s Programmable data word length (8 or 9 bits) s Receive buffer full, Transmit buffer empty and End of Transmission flags s Two receiver wake-up modes: - Address bit (MSB) - Idle line s Muting function for multiprocessor configurations s LIN compatible (if MCU clock frequency tolerance 2%) s Separate enable bits for Transmitter and Receiver s Three error detection flags: - Overrun error - Noise error - Frame error s Five interrupt sources with flags: - Transmit data register empty - Transmission complete - Receive data register full - Idle line received - Overrun error detected 10.6.3 General Description The interface is externally connected to another device by two pins (see Figure 2.): - TDO: Transmit Data Output. When the transmitter is disabled, the output pin returns to its I/O port configuration. When the transmitter is enabled and nothing is to be transmitted, the TDO pin is at high level. - RDI: Receive Data Input is the serial data input. Oversampling techniques are used for data recovery by discriminating between valid incoming data and noise. Through this pins, serial data is transmitted and received as frames comprising: - An Idle Line prior to transmission or reception - A start bit - A data word (8 or 9 bits) least significant bit first - A Stop bit indicating that the frame is complete. This interface uses two types of baud rate generator: - A conventional type for commonly-used baud rates, - An extended type with a prescaler offering a very wide range of baud rates even with non-standard oscillator frequencies. 10.6.4 LIN Protocol support For LIN applications where resynchronization is not required (application clock tolerance less than or equal to 2%) the LIN protocol can be efficiently implemented with this standard SCI.
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SERIAL COMMUNICATIONS INTERFACE (Cont'd) Figure 52. SCI Block Diagram
Write
Read
(DATA REGISTER) DR
Transmit Data Register (TDR) TDO Transmit Shift Register RDI
Received Data Register (RDR)
Received Shift Register
CR1
R8 T8 M
WAKE
-
-
-
TRANSMIT CONTROL
WAKE UP UNIT
RECEIVER CONTROL
RECEIVER CLOCK
CR2
TIE TCIE RIE ILIE TE RE RWU SBK TDRE TC RDRF IDLE OR NF FE
SR
-
SCI INTERRUPT CONTROL TRANSMITTER CLOCK TRANSMITTER RATE
fCPU
CONTROL
/16
/2
/PR BRR
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0
RECEIVER RATE CONTROL CONVENTIONAL BAUD RATE GENERATOR
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SERIAL COMMUNICATIONS INTERFACE (Cont'd) 10.6.5 Functional Description The block diagram of the Serial Control Interface, is shown in Figure 1.. It contains 6 dedicated registers: - Two control registers (CR1 & CR2) - A status register (SR) - A baud rate register (BRR) - An extended prescaler receiver register (ERPR) - An extended prescaler transmitter register (ETPR) Refer to the register descriptions in Section 0.1.8 for the definitions of each bit.
10.6.5.1 Serial Data Format Word length may be selected as being either 8 or 9 bits by programming the M bit in the CR1 register (see Figure 1.). The TDO pin is in low state during the start bit. The TDO pin is in high state during the stop bit. An Idle character is interpreted as an entire frame of "1"s followed by the start bit of the next frame which contains data. A Break character is interpreted on receiving "0"s for some multiple of the frame period. At the end of the last break frame the transmitter inserts an extra "1" bit to acknowledge the start bit. Transmission and reception are driven by their own baud rate generator.
Figure 53. Word length programming 9-bit Word length (M bit is set) Data Frame
Start Bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Possible Parity Bit Bit8
Next Data Frame
Next Stop Start Bit Bit Start Bit
Idle Frame
Break Frame
Extra '1'
Start Bit
8-bit Word length (M bit is reset) Data Frame
Start Bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6
Possible Parity Bit Bit7 Stop Bit
Next Data Frame
Next Start Bit Start Bit Extra Start Bit '1'
Idle Frame Break Frame
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SERIAL COMMUNICATIONS INTERFACE (Cont'd) 10.6.5.2 Transmitter The transmitter can send data words of either 8 or 9 bits depending on the M bit status. When the M bit is set, word length is 9 bits and the 9th bit (the MSB) has to be stored in the T8 bit in the CR1 register. Character Transmission During an SCI transmission, data shifts out least significant bit first on the TDO pin. In this mode, the DR register consists of a buffer (TDR) between the internal bus and the transmit shift register (see Figure 1.). Procedure - Select the M bit to define the word length. - Select the desired baud rate using the BRR and the ETPR registers. - Set the TE bit to assign the TDO pin to the alternate function and to send a idle frame as first transmission. - Access the SR register and write the data to send in the DR register (this sequence clears the TDRE bit). Repeat this sequence for each data to be transmitted. Clearing the TDRE bit is always performed by the following software sequence: 1. An access to the SR register 2. A write to the DR register The TDRE bit is set by hardware and it indicates: - The TDR register is empty. - The data transfer is beginning. - The next data can be written in the DR register without overwriting the previous data. This flag generates an interrupt if the TIE bit is set and the I bit is cleared in the CCR register. When a transmission is taking place, a write instruction to the DR register stores the data in the TDR register and which is copied in the shift register at the end of the current transmission. When no transmission is taking place, a write instruction to the DR register places the data directly in the shift register, the data transmission starts, and the TDRE bit is immediately set.
When a frame transmission is complete (after the stop bit or after the break frame) the TC bit is set and an interrupt is generated if the TCIE is set and the I bit is cleared in the CCR register. Clearing the TC bit is performed by the following software sequence: 1. An access to the SR register 2. A write to the DR register Note: The TDRE and TC bits are cleared by the same software sequence. Break Characters Setting the SBK bit loads the shift register with a break character. The break frame length depends on the M bit (see Figure 2.). As long as the SBK bit is set, the SCI send break frames to the TDO pin. After clearing this bit by software the SCI insert a logic 1 bit at the end of the last break frame to guarantee the recognition of the start bit of the next frame. Idle Characters Setting the TE bit drives the SCI to send an idle frame before the first data frame. Clearing and then setting the TE bit during a transmission sends an idle frame after the current word. Note: Resetting and setting the TE bit causes the data in the TDR register to be lost. Therefore the best time to toggle the TE bit is when the TDRE bit is set i.e. before writing the next byte in the DR.
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SERIAL COMMUNICATIONS INTERFACE (Cont'd) 10.6.5.3 Receiver The SCI can receive data words of either 8 or 9 bits. When the M bit is set, word length is 9 bits and the MSB is stored in the R8 bit in the CR1 register. Character reception During a SCI reception, data shifts in least significant bit first through the RDI pin. In this mode, DR register consists in a buffer (RDR) between the internal bus and the received shift register (see Figure 1.). Procedure - Select the M bit to define the word length. - Select the desired baud rate using the BRR and the ERPR registers. - Set the RE bit, this enables the receiver which begins searching for a start bit. When a character is received: - The RDRF bit is set. It indicates that the content of the shift register is transferred to the RDR. - An interrupt is generated if the RIE bit is set and the I bit is cleared in the CCR register. - The error flags can be set if a frame error, noise or an overrun error has been detected during reception. Clearing the RDRF bit is performed by the following software sequence done by: 1. An access to the SR register 2. A read to the DR register. The RDRF bit must be cleared before the end of the reception of the next character to avoid an overrun error. Break Character When a break character is received, the SCI handles it as a framing error. Idle Character When a idle frame is detected, there is the same procedure as a data received character plus an interrupt if the ILIE bit is set and the I bit is cleared in the CCR register.
Overrun Error An overrun error occurs when a character is received when RDRF has not been reset. Data can not be transferred from the shift register to the TDR register as long as the RDRF bit is not cleared. When a overrun error occurs: - The OR bit is set. - The RDR content will not be lost. - The shift register will be overwritten. - An interrupt is generated if the RIE bit is set and the I bit is cleared in the CCR register. The OR bit is reset by an access to the SR register followed by a DR register read operation. Noise Error Oversampling techniques are used for data recovery by discriminating between valid incoming data and noise. When noise is detected in a frame: - The NF is set at the rising edge of the RDRF bit. - Data is transferred from the Shift register to the DR register. - No interrupt is generated. However this bit rises at the same time as the RDRF bit which itself generates an interrupt. The NF bit is reset by a SR register read operation followed by a DR register read operation. Framing Error A framing error is detected when: - The stop bit is not recognized on reception at the expected time, following either a de-synchronization or excessive noise. - A break is received. When the framing error is detected: - the FE bit is set by hardware - Data is transferred from the Shift register to the DR register. - No interrupt is generated. However this bit rises at the same time as the RDRF bit which itself generates an interrupt. The FE bit is reset by a SR register read operation followed by a DR register read operation.
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SERIAL COMMUNICATIONS INTERFACE (Cont'd) Figure 54. SCI Baud Rate and Extended Prescaler Block Diagram
EXTENDED PRESCALER TRANSMITTER RATE CONTROL
ETPR
EXTENDED TRANSMITTER PRESCALER REGISTER
ERPR
EXTENDED RECEIVER PRESCALER REGISTER
EXTENDED PRESCALER RECEIVER RATE CONTROL EXTENDED PRESCALER
fCPU
TRANSMITTER RATE CONTROL
TRANSMITTER CLOCK
/16
/2
/PR BRR
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0 RECEIVER CLOCK RECEIVER RATE CONTROL CONVENTIONAL BAUD RATE GENERATOR
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SERIAL COMMUNICATIONS INTERFACE (Cont'd) 10.6.5.4 Conventional Baud Rate Generation than zero. The baud rates are calculated as follows: The baud rate for the receiver and transmitter (Rx and Tx) are set independently and calculated as fCPU fCPU follows: Rx = Tx = fCPU fCPU 16*ERPR 16*ETPR Rx = Tx = (32*PR)*RR (32*PR)*TR with: with: ETPR = 1,..,255 (see ETPR register) PR = 1, 3, 4 or 13 (see SCP0 & SCP1 bits) ERPR = 1,.. 255 (see ERPR register) TR = 1, 2, 4, 8, 16, 32, 64,128 10.6.5.6 Receiver Muting and Wake-up Feature (see SCT0, SCT1 & SCT2 bits) In multiprocessor configurations it is often desirable that only the intended message recipient RR = 1, 2, 4, 8, 16, 32, 64,128 should actively receive the full message contents, (see SCR0,SCR1 & SCR2 bits) thus reducing redundant SCI service overhead for All this bits are in the BRR register. all non addressed receivers. Example: If fCPU is 8 MHz (normal mode) and if The non addressed devices may be placed in PR=13 and TR=RR=1, the transmit and receive sleep mode by means of the muting function. baud rates are 19200 baud. Setting the RWU bit by software puts the SCI in Caution: The baud rate registers MUST NOT be sleep mode: written to (changed or refreshed) while the transAll the reception status bits can not be set. mitter or the receiver is enabled. All the receive interrupt are inhibited. 10.6.5.5 Extended Baud Rate Generation A muted receiver may be awakened by one of the The extended prescaler option gives a very fine following two ways: tuning on the baud rate, using a 255 value prescal- by Idle Line detection if the WAKE bit is reset, er, whereas the conventional Baud Rate Generator retains industry standard software compatibili- by Address Mark detection if the WAKE bit is set. ty. Receiver wakes-up by Idle Line detection when The extended baud rate generator block diagram the Receive line has recognised an Idle Frame. is described in the Figure 3.. Then the RWU bit is reset by hardware but the IDLE bit is not set. The output clock rate sent to the transmitter or to the receiver will be the output from the 16 divider Receiver wakes-up by Address Mark detection divided by a factor ranging from 1 to 255 set in the when it received a "1" as the most significant bit of ERPR or the ETPR register. a word, thus indicating that the message is an address. The reception of this particular word wakes Note: the extended prescaler is activated by setup the receiver, resets the RWU bit and sets the ting the ETPR or ERPR register to a value other RDRF bit, which allows the receiver to receive this word normally and to use it as an address word.
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SERIAL COMMUNICATIONS INTERFACE (Cont'd) 10.6.6 Low Power Modes Mode WAIT HALT Description No effect on SCI. SCI interrupts cause the device to exit from Wait mode. SCI registers are frozen. In Halt mode, the SCI stops transmitting/receiving until Halt mode is exited.
10.6.7 Interrupts
Interrupt Event Transmit Data Register Empty Transmission Complete Received Data Ready to be Read Overrrun Error Detected Idle Line Detected Event Flag Enable Control Bit TDRE TIE TC TCIE RDRF RIE OR IDLE ILIE Exit from Wait Yes Yes Yes Yes Yes Exit from Halt No No No No No
The SCI interrupt events are connected to the same interrupt vector (see Interrupts chapter).
These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction).
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SERIAL COMMUNICATIONS INTERFACE (Cont'd) 10.6.8 Register Description STATUS REGISTER (SR) Read Only Reset Value: 1100 0000 (C0h)
7
TDRE TC RDRF IDLE OR NF FE
Note: The IDLE bit will not be set again until the RDRF bit has been set itself (i.e. a new idle line occurs). This bit is not set by an idle line when the receiver wakes up from wake-up mode. Bit 3 = OR Overrun error. This bit is set by hardware when the word currently being received in the shift register is ready to be transferred into the RDR register while RDRF=1. An interrupt is generated if RIE=1 in the CR2 register. It is cleared by a software sequence (an access to the SR register followed by a read to the DR register). 0: No Overrun error 1: Overrun error is detected Note: When this bit is set RDR register content will not be lost but the shift register will be overwritten. Bit 2 = NF Noise flag. This bit is set by hardware when noise is detected on a received frame. It is cleared by a software sequence (an access to the SR register followed by a read to the DR register). 0: No noise is detected 1: Noise is detected Note: This bit does not generate interrupt as it appears at the same time as the RDRF bit which itself generates an interrupt. Bit 1 = FE Framing error. This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by a software sequence (an access to the SR register followed by a read to the DR register). 0: No Framing error is detected 1: Framing error or break character is detected Note: This bit does not generate interrupt as it appears at the same time as the RDRF bit which itself generates an interrupt. If the word currently being transferred causes both frame error and overrun error, it will be transferred and only the OR bit will be set. Bit 0 = Unused.
0 -
Bit 7 = TDRE Transmit data register empty. This bit is set by hardware when the content of the TDR register has been transferred into the shift register. An interrupt is generated if the TIE =1 in the CR2 register. It is cleared by a software sequence (an access to the SR register followed by a write to the DR register). 0: Data is not transferred to the shift register 1: Data is transferred to the shift register Note: data will not be transferred to the shift register as long as the TDRE bit is not reset. Bit 6 = TC Transmission complete. This bit is set by hardware when transmission of a frame containing Data, a Preamble or a Break is complete. An interrupt is generated if TCIE=1 in the CR2 register. It is cleared by a software sequence (an access to the SR register followed by a write to the DR register). 0: Transmission is not complete 1: Transmission is complete Bit 5 = RDRF Received data ready flag. This bit is set by hardware when the content of the RDR register has been transferred into the DR register. An interrupt is generated if RIE=1 in the CR2 register. It is cleared by a software sequence (an access to the SR register followed by a read to the DR register). 0: Data is not received 1: Received data is ready to be read Bit 4 = IDLE Idle line detect. This bit is set by hardware when a Idle Line is detected. An interrupt is generated if the ILIE=1 in the CR2 register. It is cleared by a software sequence (an access to the SR register followed by a read to the DR register). 0: No Idle Line is detected 1: Idle Line is detected
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SERIAL COMMUNICATIONS INTERFACE (Cont'd) CONTROL REGISTER 1 (CR1) 1: An SCI interrupt is generated whenever TC=1 in the SR register Read/Write Reset Value: Undefined Bit 5 = RIE Receiver interrupt enable. This bit is set and cleared by software. 7 0 0: interrupt is inhibited 1: An SCI interrupt is generated whenever OR=1 R8 T8 M WAKE or RDRF=1 in the SR register Bit 7 = R8 Receive data bit 8. This bit is used to store the 9th bit of the received word when M=1. Bit 6 = T8 Transmit data bit 8. This bit is used to store the 9th bit of the transmitted word when M=1. Bit 4 = M Word length. This bit determines the word length. It is set or cleared by software. 0: 1 Start bit, 8 Data bits, 1 Stop bit 1: 1 Start bit, 9 Data bits, 1 Stop bit Bit 3 = WAKE Wake-Up method. This bit determines the SCI Wake-Up method, it is set or cleared by software. 0: Idle Line 1: Address Mark CONTROL REGISTER 2 (CR2) Read/Write Reset Value: 0000 0000 (00 h)
7
TIE TCIE RIE ILIE TE RE RWU
Bit 4 = ILIE Idle line interrupt enable. This bit is set and cleared by software. 0: interrupt is inhibited 1: An SCI interrupt is generated whenever IDLE=1 in the SR register. Bit 3 = TE Transmitter enable. This bit enables the transmitter and assigns the TDO pin to the alternate function. It is set and cleared by software. 0: Transmitter is disabled, the TDO pin is back to the I/O port configuration. 1: Transmitter is enabled Note: during transmission, a "0" pulse on the TE bit ("0" followed by "1") sends a preamble after the current word. Bit 2 = RE Receiver enable. This bit enables the receiver. It is set and cleared by software. 0: Receiver is disabled. 1: Receiver is enabled and begins searching for a start bit. Bit 1 = RWU Receiver wake-up. This bit determines if the SCI is in mute mode or not. It is set and cleared by software and can be cleared by hardware when a wake-up sequence is recognized. 0: Receiver in active mode 1: Receiver in mute mode Bit 0 = SBK Send break. This bit set is used to send break characters. It is set and cleared by software. 0: No break character is transmitted 1: Break characters are transmitted Note: If the SBK bit is set to "1" and then to "0", the transmitter will send a BREAK word at the end of the current word.
0 SBK
Bit 7 = TIE Transmitter interrupt enable. This bit is set and cleared by software. 0: interrupt is inhibited 1: An SCI interrupt is generated whenever TDRE=1 in the SR register. Bit 6 = TCIE Transmission complete interrupt enable This bit is set and cleared by software. 0: interrupt is inhibited
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SERIAL COMMUNICATIONS INTERFACE (Cont'd) DATA REGISTER (DR) Read/Write Reset Value: Undefined Contains the Received or Transmitted data character, depending on whether it is read from or written to.
7
DR7 DR6 DR5 DR4 DR3 DR2 DR1
Bit 5:3 = SCT[2:0] SCI Transmitter rate divisor These 3 bits, in conjunction with the SCP1 & SCP0 bits define the total division applied to the bus clock to yield the transmit rate clock in conventional Baud Rate Generator mode.
TR dividing factor 1 2 4 8 16 32 64 128 SCT2 0 0 0 0 1 1 1 1 SCT1 0 0 1 1 0 0 1 1 SCT0 0 1 0 1 0 1 0 1
0
DR0
The Data register performs a double function (read and write) since it is composed of two registers, one for transmission (TDR) and one for reception (RDR). The TDR register provides the parallel interface between the internal bus and the output shift register (see Figure 1.). The RDR register provides the parallel interface between the input shift register and the internal bus (see Figure 1.). BAUD RATE REGISTER (BRR) Read/Write Reset Value: 00xx xxxx (XXh)
7
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2
0
SCR1 SCR0
Note: this TR factor is used only when the ETPR fine tuning factor is equal to 00h; otherwise, TR is replaced by the ETPR dividing factor. Bit 2:0 = SCR[2:0] SCI Receiver rate divisor. These 3 bits, in conjunction with the SCP1 & SCP0 bits define the total division applied to the bus clock to yield the receive rate clock in conventional Baud Rate Generator mode.
RR dividing factor 1 2 4 8 16 32 64 128 SCR2 0 0 0 0 1 1 1 1 SCR1 0 0 1 1 0 0 1 1 SCR0 0 1 0 1 0 1 0 1
Bit 7:6= SCP[1:0] First SCI Prescaler These 2 prescaling bits allow several standard clock division ranges:
PR Prescaling factor 1 3 4 13 SCP1 0 0 1 1 SCP0 0 1 0 1
Note: this RR factor is used only when the ERPR fine tuning factor is equal to 00h; otherwise, RR is replaced by the ERPR dividing factor.
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SERIAL COMMUNICATIONS INTERFACE (Cont'd) EXTENDED RECEIVE PRESCALER DIVISION REGISTER (ERPR) Read/Write Reset Value: 0000 0000 (00 h) Allows setting of the Extended Prescaler rate division factor for the receive circuit.
7 0
EXTENDED TRANSMIT PRESCALER DIVISION REGISTER (ETPR) Read/Write Reset Value:0000 0000 (00h) Allows setting of the External Prescaler rate division factor for the transmit circuit.
7
ETPR 7 ETPR 6 ETPR 5 ETPR 4 ETPR 3 ETPR 2
0
ETPR ETPR 1 0
ERPR ERPR ERPR ERPR ERPR ERPR ERPR ERPR 7 6 5 4 3 2 1 0
Bit 7:1 = ERPR[7:0] 8-bit Extended Receive Prescaler Register. The extended Baud Rate Generator is activated when a value different from 00h is stored in this register. Therefore the clock frequency issued from the 16 divider (see Figure 3.) is divided by the binary factor set in the ERPR register (in the range 1 to 255). The extended baud rate generator is not used after a reset.
Bit 7:1 = ETPR[7:0] 8-bit Extended Transmit Prescaler Register. The extended Baud Rate Generator is activated when a value different from 00h is stored in this register. Therefore the clock frequency issued from the 16 divider (see Figure 3.) is divided by the binary factor set in the ETPR register (in the range 1 to 255). The extended baud rate generator is not used after a reset.
Table 22. SCI Register Map and Reset Values
Address (Hex.) 0050h 0051h 0052h 0053h 0054h 0055h 0057h Register Label SCISR Reset Value SCIDR Reset Value SCIBRR Reset Value SCICR1 Reset Value SCICR2 Reset Value SCIERPR Reset Value SCIETPR Reset Value 7 TDRE 1 MSB x SCP1 0 R8 x TIE 0 MSB 0 MSB 0 6 TC 1 x SCP0 0 T8 x TCIE 0 0 0 5 RDRF 0 x SCT2 0 0 RIE 0 0 0 4 IDLE 0 x SCT1 0 M x ILIE 0 0 0 3 OR 0 x SCT0 0 WAKE x TE 0 0 0 2 NF 0 x SCR2 0 0 RE 0 0 0 1 FE 0 x SCR1 0 0 RWU 0 0 0 0
0 LSB x SCR0 0 0 SBK 0 LSB 0 LSB 0
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CONTROLLER AREA NETWORK (Cont'd) Figure 55. CAN Register Map
5Ah 5Bh 5Ch 5Dh 5Eh 5Fh 60h
Interrupt Status Interrupt Control Control/Status Baud Rate Prescaler Bit Timing Page Selection
6Fh
Paged Reg1 Paged Reg1 Paged Reg0 Paged Reg1 Paged Reg2 Paged Reg1 Paged Reg2 Paged Reg1 Paged Reg2 Paged Reg3 Paged Reg2 Paged Reg3 Paged Reg2 Paged Reg3 Paged Reg4 Paged Reg3 Paged Reg4 Paged Reg3 Paged Reg4 Paged Reg5 Paged Reg4 Paged Reg5 Paged Reg4 Paged Reg5 Paged Reg6 Paged Reg5 Paged Reg6 Paged Reg5 Paged Reg6 Paged Reg7 Paged Reg6 Paged Reg7 Paged Reg6 Paged Reg7 Paged Reg8 Paged Reg7 Paged Reg8 Paged Reg7 Paged Reg8 Paged Reg9 Paged Reg8 Paged Reg9 Paged Paged Reg9 Paged Reg10 Reg8 Paged Reg9 Paged Reg10 Paged Paged Reg10 Paged Reg11 Reg9 Paged Reg10 Paged Reg11 Paged Paged Reg11 Paged Reg12 Reg10 Paged Reg11 Paged Reg12 Paged Paged Reg12 Paged Reg13 Reg11 Paged Reg12 Paged Reg13 Paged Paged Reg13 Paged Reg14 Reg12 Paged Reg13 Paged Reg14 Paged Paged Reg14 Paged Reg15 Reg13 Paged Reg14 Paged Reg15 Paged Reg14 Paged Reg15 Paged Reg15 Paged Reg15
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CONTROLLER AREA NETWORK (Cont'd) Figure 56. Page Maps
PAGE 0 LIDHR LIDLR
PAGE 1 IDHR1 IDLR1 DATA01 DATA11 DATA21 DATA31 DATA41
PAGE 2 IDHR2 IDLR2 DATA02 DATA12 DATA22 DATA32 DATA42 DATA52 DATA62 DATA72
PAGE 3 IDHR3 IDLR3 DATA03 DATA13 DATA23 DATA33 DATA43 DATA53 DATA63 DATA73
PAGE 4 FHR0 FLR0 MHR0 MLR0 FHR1 FLR1 MHR1 MLR1
60h
61h
62h
63h
64h
65h
66h
67h
Reserved
DATA51 DATA61 DATA71
68h
69h
6Ah
6Bh
Reserved
6Ch
Reserved TSTR TECR RECR Diagnosis BCSR1 Buffer 1
Reserved
Reserved
6Dh
6Eh
6Fh
BCSR2 Buffer 2
BCSR3 Buffer 3 Acceptance Filters
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CONTROLLER AREA NETWORK (Cont'd) Table 23. CAN Register Map and Reset Values
Address (Hex.) 5A 5B 5C 5D 5E 5F 0 60 1 to 3 60, 64 4 0 61 1 to 3 61, 65 62 to 69 62, 66 63, 67 6E 4 Page Register Label CANISR Reset Value CANICR Reset Value CANCSR Reset Value CANBRPR Reset Value CANBTR Reset Value CANPSR Reset Value CANLIDHR Reset Value CANIDHRx Reset Value CANFHRx Reset Value CANLIDLR Reset Value CANIDLRx Reset Value CANFLRx Reset Value 7 RXIF3 0 0 0 RJW1 0 0 0 LID10 x ID10 x FIL11 x LID2 x ID2 x FIL3 x MSB x MSK11 x MSK3 x MSB 0 MSB 0 0 6 RXIF2 0 ESCI 0 BOFF 0 RJW0 0 BS22 0 0 LID9 x ID9 x FIL10 x LID1 x ID1 x FIL2 x x MSK10 x MSK2 x 0 0 0 5 RXIF1 0 RXIE 0 EPSV 0 BRP5 0 BS21 1 0 LID8 x ID8 x FIL9 x LID0 x ID0 x FIL1 x x MSK9 x MSK1 x 0 0 0 4 TXIF 0 TXIE 0 SRTE 0 BRP4 0 BS20 0 0 LID7 x ID7 x FIL8 x LRTR x RTR x FIL0 x x MSK8 x MSK0 x 0 0 0 3 SCIF 0 SCIE 0 NRTX 0 BRP3 0 BS13 0 0 LID6 x ID6 x FIL7 x LDLC3 x DLC3 x 0 x MSK7 x 0 0 0 ACC 0 2 ORIF 0 ORIE 0 FSYN 0 BRP2 0 BS12 0 PAGE2 0 LID5 x ID5 x FIL6 x LDLC2 x DLC2 x 0 x MSK6 x 0 0 0 RDY 0 1 TEIF 0 TEIE 0 WKPS 0 BRP1 0 BS11 1 PAGE1 0 LID4 x ID4 x FIL5 x LDLC1 x DLC1 x 0 x MSK5 x 0 0 0 BUSY 0 0 EPND 0 ETX 0 RUN 0 BRP0 0 BS10 1 PAGE0 0 LID3 x ID3 x FIL4 x LDLC0 x DLC0 x 0 LSB x MSK4 x 0 LSB 0 LSB 0 LOCK 0
CANDRx 1 to 3 Reset Value 4 4 0 CANMHRx Reset Value CANMLRx Reset Value CANTECR Reset Value CANRECR Reset Value 1 to 3 CANBCSRx Reset Value
6F
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10.7 8-BIT A/D CONVERTER (ADC) 10.7.1 Introduction The on-chip Analog to Digital Converter (ADC) peripheral is a 8-bit, successive approximation converter with internal sample and hold circuitry. This peripheral has up to 16 multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from up to 16 different sources. The result of the conversion is stored in a 8-bit Data Register. The A/D converter is controlled through a Control/Status Register. 10.7.2 Main Features s 8-bit conversion s Up to 16 channels with multiplexed input s Linear successive approximation s Data register (DR) which contains the results s Conversion complete status flag s On/off bit (to reduce consumption) The block diagram is shown in Figure 57. Figure 57. ADC Block Diagram 10.7.3 Functional Description 10.7.3.1 Analog Power Supply VDDA and VSSA are the high and low level reference voltage pins. In some devices (refer to device pin out description) they are internally connected to the VDD and V SS pins. Conversion accuracy may therefore be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines. See electrical characteristics section for more details.
fCPU
DIV 2
fADC
COCO
0
ADON
0
CH3
CH2
CH1
CH0
ADCCSR
4
AIN0
HOLD CONTROL
AIN1
RADC
ANALOG MUX
ANALOG TO DIGITAL CONVERTER
AINx
CADC
ADCDR
D7
D6
D5
D4
D3
D2
D1
D0
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8-BIT A/D CONVERTER (ADC) (Cont'd) 10.7.3.2 Digital A/D Conversion Result The conversion is monotonic, meaning that the result never decreases if the analog input does not and never increases if the analog input does not. If the input voltage (VAIN) is greater than or equal to V DDA (high-level voltage reference) then the conversion result in the DR register is FFh (full scale) without overflow indication. If input voltage (VAIN) is lower than or equal to VSSA (low-level voltage reference) then the conversion result in the DR register is 00h. The A/D converter is linear and the digital result of the conversion is stored in the ADCDR register. The accuracy of the conversion is described in the parametric section. RAIN is the maximum recommended impedance for an analog input signal. If the impedance is too high, this will result in a loss of accuracy due to leakage and sampling not being completed in the alloted time. 10.7.3.3 A/D Conversion Phases The A/D conversion is based on two conversion phases as shown in Figure 58: s Sample capacitor loading [duration: tLOAD] During this phase, the VAIN input voltage to be measured is loaded into the CADC sample capacitor. s A/D conversion [duration: tCONV] During this phase, the A/D conversion is computed (8 successive approximations cycles) and the CADC sample capacitor is disconnected from the analog input pin to get the optimum analog to digital conversion accuracy. While the ADC is on, these two phases are continuously repeated. At the end of each conversion, the sample capacitor is kept loaded with the previous measurement load. The advantage of this behaviour is that it minimizes the current consumption on the analog pin in case of single input channel measurement. 10.7.3.4 Software Procedure Refer to the control/status register (CSR) and data register (DR) in Section 10.7.6 for the bit definitions and to Figure 58 for the timings. ADC Configuration The total duration of the A/D conversion is 12 ADC clock periods (1/fADC=2/fCPU). The analog input ports must be configured as input, no pull-up, no interrupt. Refer to the I/O ports chapter. Using these pins as analog inputs does not affect the ability of the port to be read as a logic input. In the CSR register: - Select the CH[3:0] bits to assign the analog channel to be converted. ADC Conversion In the CSR register: - Set the ADON bit to enable the A/D converter and to start the first conversion. From this time on, the ADC performs a continuous conversion of the selected channel. When a conversion is complete - The COCO bit is set by hardware. - No interrupt is generated. - The result is in the DR register and remains valid until the next conversion has ended. A write to the CSR register (with ADON set) aborts the current conversion, resets the COCO bit and starts a new conversion. Figure 58. ADC Conversion Timings
ADON tCONV
ADCCSR WRITE OPERATION
HOLD CONTROL
tLOAD
COCO BIT SET
10.7.4 Low Power Modes
Mode WAIT HALT Description No effect on A/D Converter A/D Converter disabled. After wakeup from Halt mode, the A/D Converter requires a stabilisation time before accurate conversions can be performed.
Note: The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced power consumption when no conversion is needed and between single shot conversions. 10.7.5 Interrupts None
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8-BIT A/D CONVERTER (ADC) (Cont'd) 10.7.6 Register Description CONTROL/STATUS REGISTER (CSR) Read /Write Reset Value: 0000 0000 (00h)
7
COCO 0 ADON 0 CH3 CH2 CH1
DATA REGISTER (DR) Read Only Reset Value: 0000 0000 (00h)
0
CH0
7
D7 D6 D5 D4 D3 D2 D1
0
D0
Bit 7 = COCO Conversion Complete This bit is set by hardware. It is cleared by software reading the result in the DR register or writing to the CSR register. 0: Conversion is not complete 1: Conversion can be read from the DR register Bit 6 = Reserved. must always be cleared. Bit 5 = ADON A/D Converter On This bit is set and cleared by software. 0: A/D converter is switched off 1: A/D converter is switched on Bit 4 = Reserved. must always be cleared. Bits 3:0 = CH[3:0] Channel Selection These bits are set and cleared by software. They select the analog input to convert.
Channel Pin* AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11 AIN12 AIN13 AIN14 AIN15 CH3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 CH2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 CH1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 CH0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Bits 7:0 = D[7:0] Analog Converted Value This register contains the converted analog value in the range 00h to FFh. Note: Reading this register reset the COCO flag.
*Note: The number of pins AND the channel selection varies according to the device. Refer to the device pinout.
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8-BIT A/D CONVERTOR (ADC) (Cont'd) Table 24. ADC Register Map and Reset Values
Address (Hex.) 0070h Register Label ADCDR Reset Value ADCCSR Standard Reset Value 7 D7 0 COCO 0 0 0 6 D6 0 5 D5 0 ADON 0 0 0 0 0 4 D4 0 3 D3 0 2 D2 0 CH2 1 D1 0 CH1 0 D0 0 CH0
0071h
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11 INSTRUCTION SET
11.1 CPU ADDRESSING MODES The CPU features 17 different addressing modes which can be classified in 7 main groups:
Addressing Mode Inherent Immediate Direct Indexed Indirect Relative Bit operation Example nop ld A,#$55 ld A,$55 ld A,($55,X) ld A,([$55],X) jrne loop bset byte,#5
The CPU Instruction set is designed to minimize the number of bytes required per instruction: To do Table 25. CPU Addressing Mode Overview
Mode Inherent Immediate Short Long No Offset Short Long Short Long Short Long Relative Relative Bit Bit Bit Bit Direct Direct Direct Direct Direct Indirect Indirect Indirect Indirect Direct Indirect Direct Indirect Direct Indirect Relative Relative Indexed Indexed Indexed Indexed Indexed nop ld A,#$55 ld A,$10 ld A,$1000 ld A,(X) ld A,($10,X) ld A,($1000,X) ld A,[$10] ld A,[$10.w] ld A,([$10],X) ld A,([$10.w],X) jrne loop jrne [$10] bset $10,#7 bset [$10],#7 btjt $10,#7,skip btjt [$10],#7,skip Syntax
so, most of the addressing modes may be subdivided in two sub-modes called long and short: - Long addressing mode is more powerful because it can use the full 64 Kbyte address space, however it uses more bytes and more CPU cycles. - Short addressing mode is less powerful because it can generally only access page zero (0000h 00FFh range), but the instruction size is more compact, and faster. All memory to memory instructions use short addressing modes only (CLR, CPL, NEG, BSET, BRES, BTJT, BTJF, INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP) The ST7 Assembler optimizes the use of long and short addressing modes.
Destination
Pointer Address (Hex.)
Pointer Size (Hex.)
Length (Bytes) +0 +1
00..FF 0000..FFFF 00..FF 00..1FE 0000..FFFF 00..FF 0000..FFFF 00..1FE 0000..FFFF PC+/-127 PC+/-127 00..FF 00..FF 00..FF 00..FF 00..FF byte 00..FF byte 00..FF byte 00..FF 00..FF 00..FF 00..FF byte word byte word
+1 +2 +0 +1 +2 +2 +2 +2 +2 +1 +2 +1 +2 +2 +3
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INSTRUCTION SET OVERVIEW (Cont'd) 11.1.1 Inherent All Inherent instructions consist of a single byte. The opcode fully specifies all the required information for the CPU to process the operation.
Inherent Instruction NOP TRAP WFI HALT RET IRET SIM RIM SCF RCF RSP LD CLR PUSH/POP INC/DEC TNZ CPL, NEG MUL SLL, SRL, SRA, RLC, RRC SWAP Function No operation S/W Interrupt Wait For Interrupt (Low Power Mode) Halt Oscillator (Lowest Power Mode) Sub-routine Return Interrupt Sub-routine Return Set Interrupt Mask (level 3) Reset Interrupt Mask (level 0) Set Carry Flag Reset Carry Flag Reset Stack Pointer Load Clear Push/Pop to/from the stack Increment/Decrement Test Negative or Zero 1 or 2 Complement Byte Multiplication Shift and Rotate Operations Swap Nibbles
11.1.3 Direct In Direct instructions, the operands are referenced by their memory address. The direct addressing mode consists of two submodes: Direct (short) The address is a byte, thus requires only one byte after the opcode, but only allows 00 - FF addressing space. Direct (long) The address is a word, thus allowing 64 Kbyte addressing space, but requires 2 bytes after the opcode. 11.1.4 Indexed (No Offset, Short, Long) In this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (X or Y) with an offset. The indirect addressing mode consists of three sub-modes: Indexed (No Offset) There is no offset, (no extra byte after the opcode), and allows 00 - FF addressing space. Indexed (Short) The offset is a byte, thus requires only one byte after the opcode and allows 00 - 1FE addressing space. Indexed (long) The offset is a word, thus allowing 64 Kbyte addressing space and requires 2 bytes after the opcode. 11.1.5 Indirect (Short, Long) The required data byte to do the operation is found by its memory address, located in memory (pointer). The pointer address follows the opcode. The indirect addressing mode consists of two sub-modes: Indirect (short) The pointer address is a byte, the pointer size is a byte, thus allowing 00 - FF addressing space, and requires 1 byte after the opcode. Indirect (long) The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode.
11.1.2 Immediate Immediate instructions have two bytes, the first byte contains the opcode, the second byte contains the operand value.
Immediate Instruction LD CP BCP AND, OR, XOR ADC, ADD, SUB, SBC Load Compare Bit Compare Logical Operations Arithmetic Operations Function
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INSTRUCTION SET OVERVIEW (Cont'd) 11.1.6 Indirect Indexed (Short, Long) This is a combination of indirect and short indexed addressing modes. The operand is referenced by its memory address, which is defined by the unsigned addition of an index register value (X or Y) with a pointer value located in memory. The pointer address follows the opcode. The indirect indexed addressing mode consists of two sub-modes: Indirect Indexed (Short) The pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1FE addressing space, and requires 1 byte after the opcode. Indirect Indexed (Long) The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode. Table 26. Instructions Supporting Direct, Indexed, Indirect and Indirect Indexed Addressing Modes
Long and Short Instructions LD CP AND, OR, XOR ADC, ADD, SUB, SBC BCP Load Compare Logical Operations Arithmetic Additions/Substractions operations Bit Compare Function
11.1.7 Relative mode (Direct, Indirect) This addressing mode is used to modify the PC register value, by adding an 8-bit signed offset to it.
Available Relative Direct/Indirect Instructions JRxx CALLR Function Conditional Jump Call Relative
The relative addressing mode consists of two submodes: Relative (Direct) The offset is following the opcode. Relative (Indirect) The offset is defined in memory, which address follows the opcode.
Short Instructions Only CLR INC, DEC TNZ CPL, NEG BSET, BRES BTJT, BTJF SLL, SRL, SRA, RLC, RRC SWAP CALL, JP Clear
Function
Increment/Decrement Test Negative or Zero 1 or 2 Complement Bit Operations Bit Test and Jump Operations Shift and Rotate Operations Swap Nibbles Call or Jump subroutine
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INSTRUCTION SET OVERVIEW (Cont'd) 11.2 INSTRUCTION GROUPS The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may
Load and Transfer Stack operation Increment/Decrement Compare and Tests Logical operations Bit Operation Conditional Bit Test and Branch Arithmetic operations Shift and Rotates Unconditional Jump or Call Conditional Branch Interruption management Condition Code Flag modification LD PUSH INC CP AND BSET BTJT ADC SLL JRA JRxx TRAP SIM WFI RIM HALT SCF IRET RCF CLR POP DEC TNZ OR BRES BTJF ADD SRL JRT SUB SRA JRF SBC RLC JP MUL RRC CALL SWAP CALLR SLA NOP RET BCP XOR CPL NEG RSP
be subdivided into 13 main groups as illustrated in the following table:
Using a pre-byte The instructions are described with one to four opcodes. In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three different prebyte opcodes are defined. These prebytes modify the meaning of the instruction they precede. The whole instruction becomes: PC-2 End of previous instruction PC-1 Prebyte PC opcode PC+1 Additional word (0 to 2) according to the number of bytes required to compute the effective address
These prebytes enable instruction in Y as well as indirect addressing modes to be implemented. They precede the opcode of the instruction in X or the instruction using direct addressing mode. The prebytes are: PDY 90 Replace an X based instruction using immediate, direct, indexed, or inherent addressing mode by a Y one. PIX 92 Replace an instruction using direct, direct bit, or direct relative addressing mode to an instruction using the corresponding indirect addressing mode. It also changes an instruction using X indexed addressing mode to an instruction using indirect X indexed addressing mode. PIY 91 Replace an instruction using X indirect indexed addressing mode by a Y one.
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INSTRUCTION SET OVERVIEW (Cont'd)
Mnemo ADC ADD AND BCP BRES BSET BTJF BTJT CALL CALLR CLR CP CPL DEC HALT IRET INC JP JRA JRT JRF JRIH JRIL JRH JRNH JRM JRNM JRMI JRPL JREQ JRNE JRC JRNC JRULT JRUGE JRUGT Description Add with Carry Addition Logical And Bit compare A, Memory Bit Reset Bit Set Jump if bit is false (0) Jump if bit is true (1) Call subroutine Call subroutine relative Clear Arithmetic Compare One Complement Decrement Halt Interrupt routine return Increment Absolute Jump Jump relative always Jump relative Never jump Jump if Port B INT pin = 1 Jump if Port B INT pin = 0 Jump if H = 1 Jump if H = 0 Jump if I1:0 = 11 Jump if I1:0 <> 11 Jump if N = 1 (minus) Jump if N = 0 (plus) Jump if Z = 1 (equal) Jump if Z = 0 (not equal) Jump if C = 1 Jump if C = 0 Jump if C = 1 Jump if C = 0 Jump if (C + Z = 0) jrf * (no Port B Interrupts) (Port B interrupt) H=1? H=0? I1:0 = 11 ? I1:0 <> 11 ? N=1? N=0? Z=1? Z=0? C=1? C=0? Unsigned < Jmp if unsigned >= Unsigned > Pop CC, A, X, PC inc X jp [TBL.w] reg, M tst(Reg - M) A = FFH-A dec Y reg, M reg reg, M reg, M 1 I1 H 0 I0 N N Z Z C M 0 N N N 1 Z Z Z C 1 Function/Example A=A+M+C A=A+M A=A.M tst (A . M) bres Byte, #3 bset Byte, #3 btjf Byte, #3, Jmp1 btjt Byte, #3, Jmp1 A A A A M M M M C C Dst Src M M M M I1 H H H I0 N N N N N Z Z Z Z Z C C C
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INSTRUCTION SET OVERVIEW (Cont'd)
Mnemo JRULE LD MUL NEG NOP OR POP PUSH RCF RET RIM RLC RRC RSP SBC SCF SIM SLA SLL SRL SRA SUB SWAP TNZ TRAP WFI XOR Description Jump if (C + Z = 1) Load Multiply Negate (2's compl) No Operation OR operation Pop from the Stack Push onto the Stack Reset carry flag Subroutine Return Enable Interrupts Rotate left true C Rotate right true C Reset Stack Pointer Substract with Carry Set carry flag Disable Interrupts Shift left Arithmetic Shift left Logic Shift right Logic Shift right Arithmetic Substraction SWAP nibbles Test for Neg & Zero S/W trap Wait for Interrupt Exclusive OR A = A XOR M A M I1:0 = 10 (level 0) C <= A <= C C => A => C S = Max allowed A=A-M-C C=1 I1:0 = 11 (level 3) C <= A <= 0 C <= A <= 0 0 => A => C A7 => A => C A=A-M A7-A4 <=> A3-A0 tnz lbl1 S/W interrupt 1 1 1 0 N Z reg, M reg, M reg, M reg, M A reg, M M 1 1 N N 0 N N N N Z Z Z Z Z Z Z C C C C C A M N Z C 1 reg, M reg, M 1 0 N N Z Z C C A=A+M pop reg pop CC push Y C=0 A reg CC M M M M reg, CC 0 I1 H I0 N Z C N Z Function/Example Unsigned <= dst <= src X,A = X * A neg $10 reg, M A, X, Y reg, M M, reg X, Y, A 0 N Z N Z 0 C Dst Src I1 H I0 N Z C
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12 ELECTRICAL CHARACTERISTICS
12.1 PARAMETER CONDITIONS Unless otherwise specified, all voltages are referred to V SS. 12.1.1 Minimum and Maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA=25C and TA=TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3). 12.1.2 Typical values Unless otherwise specified, typical data are based on TA=25C, VDD=5V (for the 4.5VVDD5.5V voltage range) and V DD=3.3V (for the 3VVDD4V voltage range). They are given only as design guidelines and are not tested. 12.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 12.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 59. Figure 59. Pin loading conditions 12.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 60. Figure 60. Pin input voltage
ST7 PIN
VIN
ST7 PIN
CL
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12.2 ABSOLUTE MAXIMUM RATINGS Stresses above those listed as "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 12.2.1 Voltage Characteristics
Symbol VDD - VSS VDDA - VSSA VDDX - VDDA |VSSA - VSSx | VIN 1) & 2) VESD(HBM) VESD(MM) Supply voltage Analog reference voltage (VDDVDDA) Ratings Maximum value 6.5 6.5 50 50 VSS-0.3 to 6.5 VSS-0.3 to VDD+0.3 mV Unit V
|VDDx| and |VSSx | Variations between different digital power pins Variations between digital and analog power pins Input voltage on true open drain pin Input voltage on any other pin Electro-static discharge voltage (Human Body Model) Electro-static discharge voltage (Machine Model)
V
see Section 12.7.2 "Absolute Electrical Sensitivity" on page 127
12.2.2 Current Characteristics
Symbol IVDD IVSS IIO Ratings Total current into VDD power lines (source) 3) Total current out of VSS ground lines (sink) 3) Output current sunk by any standard I/O and control pin Output current sunk by any high sink I/O pin Output current source by any I/Os and control pin Injected current on VPP pin IINJ(PIN) 2) & 4) Injected current on RESET pin Injected current on OSC1 and OSC2 pins Injected current on any other pin 5) & 6) IINJ(PIN) 2) Total injected current (sum of all I/O and control pins) 5) Maximum value 150 150 25 50 - 25 5 5 5 5 20 mA Unit
12.2.3 Thermal Characteristics
Symbol TSTG TJ Ratings Storage temperature range Value -65 to +150 Unit C
Maximum junction temperature (see Section 13.2 "THERMAL CHARACTERISTICS" on page 142)
Notes: 1. Directly connecting the RESET and I/O pins to VDD or VSS could damage the device if an unintentional internal reset is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter). To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7k for RESET, 10k for I/Os). Unused I/O pins must be tied in the same way to VDD or VSS according to their reset configuration. 2. When the current limitation is not possible, the VIN absolute maximum rating must be respected, otherwise refer to IINJ(PIN) specification. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN118/152
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12.3 OPERATING CONDITIONS 12.3.1 General Operating Conditions
Symbol VDD fOSC Parameter Supply voltage External clock frequency Conditions see Figure 61 and Figure 62 VDD3.5V (without EEPROM) VDD4.5V (with EEPROM) VDD3.0V 1 Suffix Version TA Ambient temperature range 6 Suffix Version 7 Suffix Version 3 Suffix Version Min 3.0 Max 5.5 16 8 70 85 105 125 C Unit V MHz
0 1) 0 1)
0 -40 -40 -40
Figure 61. fOSC Maximum Operating Frequency Versus VDD Supply for devices without EEPROM 2)
fOSC [MHz]
FUNCTIONALITY GUARANTEED IN THIS AREA
16 FUNCTIONALITY NOT GUARANTEED IN THIS AREA 8 4 1 0 2.5 3 3.5 4 4.5 5 5.5 SUPPLY VOLTAGE [V] FUNCTIONALITY NOT GUARANTEED IN THIS AREA WITH RESONATOR 1)
Figure 62. fOSC Maximum Operating Frequency Versus VDD Supply for device with EEPROM 2)
fOSC [MHz] FUNCTIONALITY NOT GUARANTEED IN THIS AREA FOR TEMPERATURE HIGHER THAN 85C
FUNCTIONALITY GUARANTEED IN THIS AREA
16 FUNCTIONALITY NOT GUARANTEED IN THIS AREA 8 4 1 0 2.5 3 3.5 4 4.5 5 5.5 SUPPLY VOLTAGE [V] FUNCTIONALITY NOT GUARANTEED IN THIS AREA WITH RESONATOR 1)
Notes: 1. Guaranteed by construction. A/D operation is not guaranteed below 1MHz. 2. Operating conditions with TA=-40 to +125C.
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OPERATING CONDITIONS (Cont'd) 12.3.2 Operating Conditions with Low Voltage Detector (LVD) Subject to general operating condition for VDD, fOSC, and TA.
Symbol VIT+ VITVhyst VtPOR tg(VDD) Parameter Reset release threshold (VDD rise) Reset generation threshold (VDD fall) LVD voltage threshold hysteresis VDD rise time rate 2) Filtered glitch delay on VDD Not detected by the LVD VIT+-VIT0.02 40 Conditions Min 3.95 3.70 Typ 1) 4.15 3.90 250 Max 4.35 V 4.10 mV V/ms ns Unit
Figure 63. LVD Threshold Versus VDD and fOSC for ROM devices 2)
fOSC [MHz] DEVICE UNDER RESET IN THIS AREA 16 8 0 2.5 3 3.5 VIT-3.70 FUNCTIONALITY NOT GUARANTEED IN THIS AREA FUNCTIONAL AREA SUPPLY VOLTAGE [V] 4 4.5 5 5.5
Notes: 1. LVD typical data are based on TA=25C. They are given only as design guidelines and are not tested. 2. The minimum VDD rise time rate is needed to insure a correct device power-on and LVD reset. Not tested in production.
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12.4 SUPPLY CURRENT CHARACTERISTICS The following current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock source current consumption. To get the total deSymbol IDD(Ta) Parameter Supply current variation vs. temperature
vice consumption, the two current values must be added (except for HALT mode for which the clock is stopped).
Conditions Constant VDD and fCPU Max 10 Unit %
12.4.1 RUN and SLOW Modes
Symbol Parameter 4.5VVDD5.5V Supply current in RUN mode (see Figure 64)
3)
Conditions fOSC=1MHz, fCPU=500kHz fOSC=4MHz, fCPU=2MHz fOSC=16MHz, fCPU=8MHz fOSC=1MHz, fCPU=31.25kHz fOSC=4MHz, fCPU=125kHz fOSC=16MHz, fCPU=500kHz fOSC=1MHz, fCPU=500kHz fOSC=4MHz, fCPU=2MHz fOSC=16MHz, fCPU=8MHz fOSC=1MHz, fCPU=31.25kHz fOSC=4MHz, fCPU=125kHz fOSC=16MHz, fCPU=500kHz
Typ 1) 2.5 6.5 14.5 0.3 0.8 1.8 1.6 3.6 8 0.15 0.45 1
Max 2) 4 9 20 0.5 2.0 3.0 2.4 5.4 12 0.3 0.9 1.5
Unit
Supply current in SLOW mode 4) (see Figure 65) IDD Supply current in RUN mode 3) (see Figure 64) Supply current in SLOW mode 4) (see Figure 65)
mA
Figure 64. Typical IDD in RUN vs. fCPU
IDD [mA] 20 8MHz 15 4MHz 2MHz
3VVDD3.6V
Figure 65. Typical IDD in SLOW vs. fCPU
IDD [mA] 2.5 500kHz 2 125kHz 31.25kHz 1.5
500kHz
10 1
5 0.5
0 3 3.5 4 4.5 5 5.5 VDD [V]
0 3 3.5 4 4.5 5 5.5 VDD [V]
Notes: 1. Typical data are based on TA=25C, VDD=5V (4.5VVDD5.5V range) and VDD=3.3V (3VVDD3.6V range). 2. Data based on characterization results, tested in production at VDD max. and fCPU max. 3. CPU running with memory access, all I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals switched off; clock input (OSC1) driven by external square wave, LVD disabled. 4. SLOW mode selected with fCPU based on fOSC divided by 32. All I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals switched off; clock input (OSC1) driven by external square wave, LVD disabled.
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SUPPLY CURRENT CHARACTERISTICS (Cont'd) 12.4.2 WAIT and SLOW WAIT Modes
Symbol Parameter 4.5VVDD5.5V Supply current in WAIT mode 3) (see Figure 66) Supply current in SLOW WAIT mode 4) (see Figure 67) IDD Supply current in WAIT mode 3) (see Figure 66) Supply current in SLOW WAIT mode 4) (see Figure 67) Conditions fOSC=1MHz, fCPU=500kHz fOSC=4MHz, fCPU=2MHz fOSC=16MHz, fCPU=8MHz fOSC=1MHz, fCPU=31.25kHz fOSC=4MHz, fCPU=125kHz fOSC=16MHz, fCPU=500kHz fOSC=1MHz, fCPU=500kHz fOSC=4MHz, fCPU=2MHz fOSC=16MHz, fCPU=8MHz fOSC=1MHz, fCPU=31.25kHz fOSC=4MHz, fCPU=125kHz fOSC=16MHz, fCPU=500kHz Typ 1) 1.25 3.2 5.2 0.2 0.6 1.2 0.7 1.6 2.7 0.1 0.3 0.6 Max 2) 2 5 9 0.35 1 2 1 2.6 4.5 0.15 0.5 1 Unit
mA
Figure 66. Typical IDD in WAIT vs. f CPU
IDD [mA] 7 6 5 8MHz 2MHz 500kHz
3VVDD3.6V
Figure 67. Typical IDD in SLOW-WAIT vs. fCPU
IDD [mA] 1.5 500kHz 125kHz 31.25kHz
1 4 3 0.5 2 1 0 3 3.5 4 4.5 5 5.5 VDD [V] 0 3 3.5 4 4.5 5 5.5 VDD [V]
Notes: 1. Typical data are based on TA=25C, VDD=5V (4.5VVDD5.5V range) and VDD=3.3V (3VVDD3.6V range). 2. Data based on characterization results, tested in production at VDD max. and fCPU max. 3. All I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals switched off; clock input (OSC1) driven by external square wave, LVD disabled. 4. SLOW-WAIT mode selected with fCPU based on fOSC divided by 32. All I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals switched off; clock input (OSC1) driven by external square wave, LVD disabled.
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SUPPLY CURRENT CHARACTERISTICS (Cont'd) 12.4.3 HALT and ACTIVE-HALT Modes
Symbol IDD Parameter Supply current in HALT mode 2) Conditions 3.0VVDD VDD5.5V
3)
Typ 1)
Max
Unit
-40CTA+105C 40CTA+125C
0
50
10 50
150
A
Supply current in ACTIVE-HALT mode
12.4.4 Supply and Clock Managers The previous current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock
Symbol IDD(CK) IDD(LVD) Parameter Supply current of resonator oscillator 6) & 7) LVD supply current
source current consumption. To get the total device consumption, the two current values must be added (except for HALT mode).
Conditions HALT mode Typ 4) 600 100 Max 5) 850 150 Unit A
12.4.5 On-Chip Peripheral
Symbol IDD(TIM) Parameter 16-bit Timer supply current 8) SPI supply current 9) ADC supply current when converting 10) Conditions fCPU=8MHz fCPU=8MHz fADC=4MHz VDD=3.3V Typ Unit
50 150 250 350 800 1100 A
VDD=5.0V
VDD=3.3V VDD=5.0V VDD=3.3V
IDD(SPI) IDD(ADC)
VDD=5.0V
Notes: 1. Typical data are based on TA=25C. 2. All I/O pins in input mode with a static value at VDD or VSS (no load), LVD disabled. 3. Data based on design simulation and/or technology characteristics, not tested in production. All I/O pins in input mode with a static value at VDD or VSS (no load); clock input (OSC1) driven by external square wave, LVD disabled. 4. Typical data are based on TA=25C, VDD=5V. 5. Data based on characterization results, not tested in production. 6. Data based on characterization results done with the typical external components, not tested in production. 7. As the oscillator is based on a current source, the consumption does not depend on the voltage. 8. Data based on a differential IDD measurement between reset configuration (timer counter running at fCPU/4) and timer counter stopped (selecting external clock capability). Data valid for one timer. 9. Data based on a differential IDD measurement between reset configuration and a permanent SPI master communication (data sent equal to 55h). 10. Data based on a differential IDD measurement between reset configuration and continuous A/D conversions.
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12.5 CLOCK AND TIMING CHARACTERISTICS Subject to general operating condition for VDD, fOSC, and TA. 12.5.1 General Timings
Symbol tc(INST) tv(IT) Parameter Instruction cycle time Interrupt reaction time tv(IT) = tc(INST) + 10
2)
Conditions fCPU=8MHz fCPU=8MHz
Min 2 250 10 1.25
Typ 1) 4 500
Max 12 1500 22 2.75
Unit tCPU ns tCPU s
12.5.2 External Clock Source
Symbol VOSC1H VOSC1L tw(OSC1H) tw(OSC1L) tr(OSC1) tf(OSC1) ROBP Parameter OSC1 input pin high level voltage OSC1 input pin low level voltage OSC1 high or low time 3) OSC1 rise or fall time 3) Oscillator bypass external resistor 1 see Figure 68 Conditions Min 0.7xVDD VSS 15 ns 15 k Typ Max VDD 0.3xVDD Unit V
Figure 68. Typical Application with an External Clock Source
90% VOSC1H 10%
VOSC1L tr(OSC1) tf(OSC1) tw(OSC1H) tw(OSC1L)
12.5.3 Crystal and Ceramic Resonator Oscillators
Symbol fOSC CL1, CL2 tSTART Parameter Oscillator Frequency Load capacitance 4) Oscillator start-up time RS=100 5) Conditions Min 4 12 Max 16 21 Unit MHz pF
Depends on resonator quality. A typical value is 10ms
Notes: 1. Data based on typical application software. 2. Time measured between interrupt event and interrupt vector fetch. tc(INST) is the number of tCPU cycles needed to finish the current instruction execution. 3. Data based on design simulation and/or technology characteristics, not tested in production. 4. CL1 (resp.CL2) is load capacitance on OSC1 (resp. OSC2) pin. 5. RS is the equivalent serial resistance of the crystal or ceramic resonator.
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12.6 MEMORY CHARACTERISTICS Subject to general operating condition for VDD, fOSC, and TA unless otherwise specified. 12.6.1 RAM and Hardware Registers
Symbol VRM Parameter Data retention mode
1)
Conditions HALT mode (or RESET)
Min 1.6
Typ
Max
Unit V
12.6.2 EEPROM Data Memory
Symbol tprog Parameter Programming time (for 1 up to 16 bytes at a time) Data retention 3) Write erase cycles 3) Conditions -40CTA+85C Min Typ Max Unit
10 15
20
-40CTA+125C
TA=+55C 2) TA=+25C
ms
Years
tret
NRW
300 000
Cycles
12.6.3 EPROM Program Memory
Symbol WERASE UV lamp Parameter Conditions Lamp wavelength 2537A UV lamp is placed 1 inch from the device window without any interposed filters TA=+55C 2) Min Typ 15 Max Unit Watt.sec /cm2 20 min years
terase tret
Erase Time
4)
15 20
Data retention 3)
Notes: 1. Minimum VDD supply voltage without losing data stored into RAM in HALT mode or under RESET) or into hardware registers (only in HALT mode). Guaranteed by construction, not tested in production. 2. The data retention time increase when the TA decreases. 3. Data based on reliability test results and monitored in production. 4. Data given only as guidelines.
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12.7 EMC CHARACTERISTICS Susceptibility tests are performed on a sample basis during product characterization. 12.7.1 Functional EMS (Electro Magnetic Susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by two electro magnetic events until a failure occurs (indicated by the LEDs). ESD: Electro-Static Discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 1000-4-2 standard. s FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V DD and VSS through a 100pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 1000-44 standard. A device reset allows normal operations to be resumed.
s
Symbol VFESD
Parameter Voltage limits to be applied on any I/O pin to induce a functional disturbance
Conditions VDD=5V, TA=+25C, fOSC=8MHz conforms to IEC 1000-4-2
Neg 1)
Pos 1)
Unit
-1 -4
1 kV 4
VFFTB
Fast transient voltage burst limits to be apVDD=5V, TA=+25C, fOSC=8MHz plied through 100pF on VDD and VDD pins conforms to IEC 1000-4-4 to induce a functional disturbance
Figure 69. EMC Recommended star network power supply connection 2)
ST72XXX 10nF 0.1F
ST7 DIGITAL NOISE FILTERING
VDD
VSS
VDD
POWER SUPPLY SOURCE
VSSA
EXTERNAL NOISE FILTERING
VDDA 0.1F
Notes: 1. Data based on characterization results, not tested in production. 2. The suggested 10nF and 0.1F decoupling capacitors on the power supply lines are proposed as a good price vs. EMC performance tradeoff. They have to be put as close as possible to the device power supply pins. Other EMC recommendations are given in other sections (I/Os, RESET, OSCx pin characteristics).
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EMC CHARACTERISTICS (Cont'd) 12.7.2 Absolute Electrical Sensitivity Based on three different tests (ESD, LU and DLU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, refer to the AN1181 ST7 application note. 12.7.2.1 Electro-Static Discharge (ESD) Electro-Static Discharges (3 positive then 3 negative pulses separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends of the number of supply pins of the device (3 parts*(n+1) supply pin). Two models are usually simulated: Human Body Model and Machine Model. This test conforms to the JESD22-A114A/A115A standard. See Figure 70 and the following test sequences. Human Body Model Test Sequence - C L is loaded through S1 by the HV pulse generator. - S1 switches position from generator to R. - A discharge from CL through R (body resistance) to the ST7 occurs. - S2 must be closed 10 to 100ms after the pulse delivery period to ensure the ST7 is not left in charge state. S2 must be opened at least 10ms prior to the delivery of the next pulse. Absolute Maximum Ratings
Symbol VESD(HBM) Ratings Electro-static discharge voltage (Human Body Model) Electro-static discharge voltage (Machine Model)
Machine Model Test Sequence - CL is loaded through S1 by the HV pulse generator. - S1 switches position from generator to ST7. - A discharge from CL to the ST7 occurs. - S2 must be closed 10 to 100ms after the pulse delivery period to ensure the ST7 is not left in charge state. S2 must be opened at least 10ms prior to the delivery of the next pulse. - R (machine resistance), in series with S2, ensures a slow discharge of the ST7.
Conditions TA=+25C TA=+25C
Maximum value 1) Unit
2500 V TBD
VESD(MM)
Figure 70. Typical Equivalent ESD Circuits
S1 R=1500 S1
R=10k~10M
HIGH VOLTAGE PULSE GENERATOR
CL=100pF
ST7
S2
HIGH VOLTAGE PULSE GENERATOR CL=200pF
ST7
S2
HUMAN BODY MODEL
MACHINE MODEL
Notes: 1. Data based on characterization results, not tested in production.
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EMC CHARACTERISTICS (Cont'd) 12.7.2.2 Static and Dynamic Latch-Up s LU: 3 complementary static tests are required on 10 parts to assess the latch-up performance. A supply overvoltage (applied to each power supply pin), a current injection (applied to each input, output and configurable I/O pin) and a power supply switch sequence are performed on each sample. This test conforms to the EIA/ JESD 78 IC latch-up standard. For more details, refer to the AN1181 ST7 application note.
s
DLU: Electro-Static Discharges (one positive then one negative test) are applied to each pin of 3 samples when the micro is running to assess the latch-up performance in dynamic mode. Power supplies are set to the typical values, the oscillator is connected as near as possible to the pins of the micro and the component is put in reset mode. This test conforms to the IEC1000-4-2 and SAEJ1752/3 standards and is described in Figure 71. For more details, refer to the AN1181 ST7 application note.
Electrical Sensitivities
Symbol LU Parameter Static latch-up class TA=+25C TA=+85C Conditions Class 1)
A A TBD
DLU
Dynamic latch-up class
VDD=5.5V, fOSC=4MHz, TA=+25C
Figure 71. Simplified Diagram of the ESD Generator for DLU
RCH=50M RD=330
DISCHARGE TIP
VDD VSS
CS=150pF ESD GENERATOR 2)
HV RELAY
ST7
DISCHARGE RETURN CONNECTION
Notes: 1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the JEDEC criteria (international standard). 2. Schaffner NSG435 with a pointed test finger.
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EMC CHARACTERISTICS (Cont'd) 12.7.3 ESD Pin Protection Strategy To protect an integrated circuit against ElectroStatic Discharge the stress must be controlled to prevent degradation or destruction of the circuit elements. The stress generally affects the circuit elements which are connected to the pads but can also affect the internal devices when the supply pads receive the stress. The elements to be protected must not receive excessive current, voltage or heating within their structure. An ESD network combines the different input and output ESD protections. This network works, by allowing safe discharge paths for the pins subjected to ESD stress. Two critical ESD stress cases are presented in Figure 72 and Figure 73 for standard pins and in Figure 74 and Figure 75 for true open drain pins.
Standard Pin Protection To protect the output structure the following elements are added: - A diode to VDD (3a) and a diode from VSS (3b) - A protection device between VDD and V SS (4) To protect the input structure the following elements are added: - A resistor in series with the pad (1) - A diode to VDD (2a) and a diode from VSS (2b) - A protection device between VDD and V SS (4)
Figure 72. Positive Stress on a Standard Pad vs. VSS
VDD VDD
(3a)
(2a)
(1) OUT (4) IN
Main path Path to avoid
(3b) (2b)
VSS
VSS
Figure 73. Negative Stress on a Standard Pad vs. VDD
VDD VDD
(3a)
(2a)
(1) OUT (4) IN
Main path
(3b) (2b)
VSS
VSS
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EMC CHARACTERISTICS (Cont'd) True Open Drain Pin Protection The centralized protection (4) is not involved in the discharge of the ESD stresses applied to true open drain pads due to the fact that a P-Buffer and diode to V DD are not implemented. An additional local protection between the pad and V SS (5a & 5b) is implemented to completely absorb the positive ESD discharge. Multisupply Configuration When several types of ground (VSS, VSSA,...) and power supply (VDD, VDDA,...) are available for any reason (better noise immunity...), the structure shown in Figure 76 is implemented to protect the device against ESD.
Figure 74. Positive Stress on a True Open Drain Pad vs. VSS
VDD VDD
Main path Path to avoid
(1) OUT (4) IN
(5a)
(3b)
(2b)
(5b)
VSS
VSS
Figure 75. Negative Stress on a True Open Drain Pad vs. VDD
VDD VDD
Main path
(1) OUT (4) IN
(3b)
(3b)
(2b)
(3b)
VSS
VSS
Figure 76. Multisupply Configuration
VDD VDDA
VDDA
VSS
BACK TO BACK DIODE BETWEEN GROUNDS
VSSA
VSSA
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12.8 I/O PORT PIN CHARACTERISTICS 12.8.1 General Characteristics Subject to general operating condition for VDD, fOSC, and TA unless otherwise specified.
Symbol VIL VIH Vhys IL IS RPU CIO tf(IO)out tr(IO)out tw(IT)in Parameter Input low level voltage
2)
Conditions
Min 0.7xVDD
Typ 1)
Max 0.3xVDD
Unit V mV
Input high level voltage 2) Schmitt trigger voltage hysteresis 3) Input leakage current Static current consumption 4) Weak pull-up equivalent resistor 5) IO pin capacitance Output high to low level fall time External interrupt pulse time 6) CL=50pF Output low to high level rise time 2) Between 10% and 90%
2)
400 VSSVINVDD Floating input mode VIN=VSS VDD=5V 60 5 25 25 1 1 200 240
A k pF ns tCPU
Figure 77. Two typical Applications with unused I/O Pin
VDD 10k
ST72XXX
10k UNUSED I/O PORT UNUSED I/O PORT
ST72XXX Notes: 1. Unless otherwise specified, typical data are based on TA=25C and VDD=5V. 2. Data based on characterization results, not tested in production. 3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested. 4. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or an external pull-up or pull-down resistor (see Figure 77). Data based on design simulation and/or technology characteristics, not tested in production. 5. The RPU pull-up equivalent resistor is based on a resistive transistor. This data is based on characterization results, not tested in production. 6. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external interrupt source.
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I/O PORT PIN CHARACTERISTICS (Cont'd) 12.8.2 Output Driving Current Subject to general operating condition for VDD, fOSC, and TA unless otherwise specified.
Symbol Parameter Output low level voltage for a standard I/O pin when 8 pins are sunk at same time (see Figure 78) VDD=5V Output low level voltage for a high sink I/O pin when 4 pins are sunk at same time (see Figure 79) Output high level voltage for an I/O pin when 8 pins are sourced at same time (see Figure 80) Conditions IIO=+5mA IIO=+2mA IIO=+20mA IIO=+8mA IIO=-5mA IIO=-2mA VDD-2.0 VDD-0.8 Min Max 1.3 0.4 1.3 0.4 V Unit
VOL 1)
VOH 2)
Figure 78. Typical VOL at VDD=5V (standard)
Vol [V] (Vdd=5V) 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 2 4 Iio [mA] 6 8 Ta=125C Ta=25C Ta=85C Ta=-40C
Figure 80. Typical VOH at VDD=5V
Voh [V] (Vdd=5V) 1.5 Ta=-40C Ta=25C Ta=85C Ta=125C
1
0.5
0 -8 -6 -4 Iio [mA] -2 0
Figure 79. Typical VOL at VDD=5V (high-sink)
Vol [V] (Vdd=5V) 2 1.5 1 0.5 0 0 10 20 Iio [mA] 30 40 Ta=-40C Ta=25C Ta=85C Ta=125C
Notes: 1. The IIO current sunk must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. The IIO current sourced must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. True open drain I/O pins does not have VOH.
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12.9 CONTROL PIN CHARACTERISTICS 12.9.1 Asynchronous RESET Pin Subject to general operating condition for VDD, fOSC, and TA unless otherwise specified.
Symbol VIL VIH Vhys RON Parameter Input low level voltage
2)
Conditions
Min 0.7xVDD
Typ 1)
Max 0.3xVDD
Unit V mV
Input high level voltage 2) Schmitt trigger voltage hysteresis 3) Weak pull-up equivalent resistor
4)
400 VIN=VSS VDD=5V 20 1 20 60 Watchdog reset source
k s s
tw(RSTL)out Generated reset pulse duration th(RSTL)in External reset pulse hold time
Figure 81. Typical Application with RESET pin 5)
VDD VDD RON 0.1F EXTERNAL RESET CIRCUIT 0.1F 4.7k RESET VDD ST72XXX
INTERNAL RESET CONTROL
WATCHDOG RESET LVD RESET
12.9.2 VPP Pin Subject to general operating condition for VDD, fOSC, and TA unless otherwise specified.
Symbol VIL VIH Parameter Input low level voltage
6)
Conditions
Min VSS VDD-0.1
Max 0.2 12.6
Unit
V
Input high level voltage 6)
Figure 82. Two typical Applications with VPP Pin 7)
VPP PROGRAMMING TOOL 4.7k VPP
ST72XXX
ST72XXX
Notes: 1. Unless otherwise specified, typical data are based on TA=25C and VDD=5V. 2. Data based on characterization results, not tested in production. 3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested. 4. The RON pull-up equivalent resistor is based on a resistive transistor. This data is based on characterization results, not tested in production. 5. The reset network protects the device against parasitic resets, especially in a noisy environment. 6. Data based on design simulation and/or technology characteristics, not tested in production. 7. When the in-circuit programming mode is not required by the application VPP pin must be tied to VSS.
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12.10 TIMER PERIPHERAL CHARACTERISTICS
SC ,
Subject to general operating condition for VDD, fOand TA unless otherwise specified.
Refer to I/O port characteristics for more details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output...).
12.10.1 Watchdog Timer
Symbol tw(WDG) Parameter Watchdog time-out duration Conditions Min 12,288 fCPU=8MHz 1.54 Typ Max 786,432 98.3 Unit tCPU ms
12.10.2 8-Bit PWM-ART Auto-Reload Timer
Symbol Parameter Conditions Min 1 fCPU=8MHz 125 0 0 fCPU/2 fCPU/2 8 VDD=5V, Res=8-bits 20 Typ Max Unit tCPU ns MHz bit mV
tres(PWM) PWM resolution time fEXT fPWM VOS ART external clock frequency PWM repetition rate
ResPWM PWM resolution PWM/DAC output step voltage
12.10.3 16-Bit Timer
Symbol Parameter Conditions Min 1 2 fCPU=8MHz 250 0 0 fCPU/4 fCPU/4 16 Typ Max Unit tCPU tCPU ns MHz MHz bit
tw(ICAP)in Input capture pulse time tres(PWM) PWM resolution time fEXT fPWM Timer external clock frequency PWM repetition rate
ResPWM PWM resolution
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12.11 COMMUNICATIONS INTERFACE CHARACTERISTICS 12.11.1 SPI - Serial Peripheral Interface Subject to general operating condition for V DD, fOSC , and TA unless otherwise specified.
Symbol fSCK 1/tc(SCK) tr(SCK) tf(SCK) tsu(SS) th(SS) tw(SCKH) tw(SCKL) tsu(MI) tsu(SI) th(MI) th(SI) ta(SO) tdis(SO) tv(SO) th(SO) tv(MO) th(MO) Parameter Master SPI clock frequency fCPU=8MHz Slave fCPU=8MHz SPI clock rise and fall time SS setup time SS hold time SCK high and low time Data input setup time Data input hold time Data output access time Data output disable time Data output valid time Data output hold time Data output valid time Data output hold time Slave Slave Master Slave Master Slave Master Slave Slave Slave Slave (after enable edge) Master (before capture edge) 0 0.25 0.25 tCPU
Refer to I/O port characteristics for more details on the input/output alternate function characteristics (SS, SCK, MOSI, MISO).
Conditions Min fCPU/128 0.0625 0 Max fCPU/4 2 fCPU/2 4 Unit
MHz
see I/O port pin description 120 120 100 90 100 100 100 100 0 120 240 120
ns
Figure 83. SPI Slave Timing Diagram with CPHA=0 3)
SS INPUT tsu(SS) SCK INPUT CPHA=0 CPOL=0 CPHA=0 CPOL=1 ta(SO) MISO OUTPUT tw(SCKH) tw(SCKL) tv(SO) th(SO) tr(SCK) tf(SCK)
LSB OUT
tc(SCK)
th(SS)
tdis(SO)
see note 2
see note 2
MSB OUT
BIT6 OUT
tsu(SI)
th(SI)
MOSI INPUT
MSB IN
BIT1 IN
LSB IN
Notes: 1. Data based on design simulation and/or characterisation results, not tested in production. 2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its alternate function capability released. In this case, the pin status depends on the I/O port configuration. 3. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.
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COMMUNICATIONS INTERFACE CHARACTERISTICS (Cont'd) Figure 84. SPI Slave Timing Diagram with CPHA=11)
SS INPUT tsu(SS) SCK INPUT CPHA=0 CPOL=0 CPHA=0 CPOL=1 ta(SO) tw(SCKH) tw(SCKL) tv(SO) th(SO) tr(SCK) tf(SCK)
LSB OUT
tc(SCK)
th(SS)
tdis(SO)
MISO OUTPUT
see note 2
HZ
MSB OUT
BIT6 OUT
see note 2
tsu(SI)
th(SI)
MOSI INPUT
MSB IN
BIT1 IN
LSB IN
Figure 85. SPI Master Timing Diagram 1)
SS INPUT tc(SCK) CPHA=0 CPOL=0 SCK INPUT CPHA=0 CPOL=1 CPHA=1 CPOL=0 CPHA=1 CPOL=1 tw(SCKH) tw(SCKL) tsu(MI) MISO INPUT tv(MO) th(MI) tr(SCK) tf(SCK)
MSB IN
BIT6 IN
LSB IN
th(MO)
MOSI OUTPUT see note 2
MSB OUT
BIT6 OUT
LSB OUT
see note 2
Notes: 1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD. 2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its alternate function capability released. In this case, the pin status depends of the I/O port configuration.
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COMMUNICATIONS INTERFACE CHARACTERISTICS (Cont'd) 12.11.2 SCI - Serial Communications Interface Subject to general operating condition for VDD, fOSC , and TA unless otherwise specified.
Symbol Parameter fCPU Accuracy vs. Standard
Refer to I/O port characteristics for more details on the input/output alternate function characteristics (RDI and TDO).
Conditions Prescaler Conventional Mode TR (or RR)=64, PR=13 TR (or RR)=16, PR=13 TR (or RR)= 8, PR=13 TR (or RR)= 4, PR=13 TR (or RR)= 2, PR=13 TR (or RR)= 8, PR= 3 TR (or RR)= 1, PR=13 Extended Mode ETPR (or ERPR) = 13 Standard Baud Rate Unit
fTx fRx
~0.16% Communication frequency 8MHz
~300.48 300 1200 ~1201.92 2400 ~2403.84 4800 ~4807.69 9600 ~9615.38 10400 ~10416.67 19200 ~19230.77 38400 ~38461.54 14400 ~14285.71
Hz
~0.79%
Extended Mode ETPR (or ERPR) = 35
12.11.3 CAN - Controller Area Network Interface Subject to general operating condition for VDD, fOSC , and TA unless otherwise specified. Refer to I/O port characteristics for more details on
Symbol tp(RX:TX) Parameter CAN controller propagation time
the input/output alternate function characteristics (CANTX and CANRX).
Min Typ Max 60 Unit ns
Conditions
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12.12 8-BIT ADC CHARACTERISTICS Subject to general operating condition for VDD, fOSC, and TA unless otherwise specified.
Symbol fADC VAIN RAIN RADC CADC tSTAB Parameter ADC clock frequency Conversion range voltage External input resistor Internal input resistor Internal sample and hold capacitor Stabilization time after ADC enable Sample capacitor loading time Hold conversion time fCPU=8MHz, fADC=4MHz 1.5 6 0
4) 2)
Conditions
Min VSSA
Typ 1)
Max 4 VDDA 15 3)
Unit MHz V k k pF
s
s 1/fADC s 1/fADC
tLOAD
tCONV
1 4 2.250 9
Figure 86. Typical Application with ADC
VDD
SAMPLING SWITCH
VT 0.6V RAIN VAIN CIO 0.1F VDD 1k VDDA VT 0.6V IL 1A RADC CADC 0.1F AINx
0.1F VSSA
ST72XXX
Notes: 1. Unless otherwise specified, typical data are based on TA=25C and VDD-VSS=5V. They are given only as design guidelines and are not tested. 2. When VDDA and VSSA pins are not available on the pinout, the ADC refer to VDD and VSS. 3. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10k). Data based on characterization results, not tested in production. 4. The stabilization time of the AD converter is masked by the first tLOAD. The first conversion after the enable is then always valid.
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ADC CHARACTERISTICS (Cont'd) ADC Accuracy with V DD=5.0V
Symbol |ET| EO EG |ED| |EL| Offset Parameter Total unadjusted error error 2) fCPU=8MHz, fADC=4MHz 1)
2) 2)
Conditions
Min -1 -0.5
Max 1.5 1 0.5 1 1
Unit
Gain Error 2) Differential linearity error Integral linearity error 2)
LSB
Figure 87. ADC Accuracy Characteristics
Digital Result ADCDR 255 254 253 1LSB IDE AL V -V DDA SSA = ---------------------------------------256 (2) ET 7 6 5 4 3 2 1 0 1 VSSA 2 3 4 1 LSBIDEAL Vin (LSBIDEAL) 5 6 7 253 254 255 256 VDDA EO EL ED (3) (1) EG (1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line
ET=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO=Offset Error: deviation between the first actual transition and the first ideal one. EG=Gain Error: deviation between the last ideal transition and the last actual one. ED=Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL=Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line.
Notes: 1. Data based on characterization results over the whole temperature range, monitored in production. 2. ADC Accuracy vs. Negative Injection Current: For IINJ-=0.8mA, the typical leakage induced inside the die is 1.6A and the effect on the ADC accuracy is a loss of 1 LSB for each 10K increase of the external analog source impedance. This effect on the ADC accuracy has been observed under worst-case conditions for injection: - negative injection - injection to an Input with analog capability, adjacent to the enabled Analog Input - at 5V VDD supply, and worst case temperature.
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13 PACKAGE CHARACTERISTICS
13.1 PACKAGE MECHANICAL DATA Figure 88. 64-Pin Thin Quad Flat Package
D D1 A1
A A2
Dim. A A1 A2
mm Min 0.05 1.35 0.30 0.09 16.00 14.00 16.00 14.00 0.80 0 0.45 3.5 1.00 64 7 0 Typ Max 1.60 0.15 0.002 Min
inches Typ Max 0.063 0.006
1.40 1.45 0.053 0.055 0.057 0.37 0.45 0.012 0.015 0.018 0.20 0.004 0.630 0.551 0.630 0.551 0.031 3.5 0.039 7 0.008
b
b c D
e E1 E
D1 E E1 e L
0.60 0.75 0.018 0.024 0.030 Number of Pins
L L1 c h
L1 N
Figure 89. 64-Pin Epoxy Thin Quad Flat Package
P
Dim A L1 L n G A1 B E e G L B L1 n P A1 A ETQFP64 N 0.50 1.10 0.35 1.10 Number of Pins 64 (4x16) e mm Min Typ Max 2.40 0.60 Min inches Typ Max 0.095 0.024
0.25 0.38 0.50 0.010 0.015 0.020 15.80 16.00 16.20 0.622 0.630 0.638 0.80 13.10 0.020 0.043 0.013 0.043 0.031 0.515
E1 12.20 12.35 12.50 0.480 0.486 0.492
Note: "QUALIFICATION OR VOLUME PRODUCTION OF DEVICES USING EPOXY PACKAGES (ESO/EDIL/EQFP) IS NOT AUTHORIZED It is expressly specified that qualification and/or volume production of devices using the package E.... in any applications is not authorized. Usage in any application is strictly restricted to development purpose. Similar devices are available in plastic package mechanically compatible to the epoxy package for qualification
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and volume production."
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13.2 THERMAL CHARACTERISTICS
Symbol RthJA PD TJmax
Ratings Package thermal resistance (junction to ambient) TQFP64 Power dissipation 1) Maximum junction temperature 2)
Value 60 500 150
Unit C/W mW C
Notes: 1. The power dissipation is obtained from the formula PD=PINT+PPORT where PINT is the chip internal power (IDDxVDD) and PPORT is the port power dissipation determined by the user. 2. The average chip-junction temperature can be obtained from the formula TJ = TA + PD x RthJA.
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13.3 SOLDERING AND GLUEABILITY INFORMATION Recommended soldering information given only as design guidelines. Figure 90. Recommended Wave Soldering Profile (with 37% Sn and 63% Pb)
250 200 150 Temp. [C] 100 50 0 20 40 60 80 100 120 140 160 PREHEATING PHASE Time [sec] 80C 5 sec SOLDERING PHASE COOLING PHASE (ROOM TEMPERATURE)
Figure 91. Recommended Reflow Soldering Oven Profile (MID JEDEC)
250 200 150 Temp. [C] 100 50 0 100 200 300 400
ramp up 2C/sec for 50sec ramp down natural 2C/sec max 90 sec at 125C 150 sec above 183C Tmax=220+/-5C for 25 sec
Time [sec]
Recommended glue for SMD plastic packages dedicated to molding compound with silicone: s Heraeus: PD945, PD955 s Loctite: 3615, 3298
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14 DEVICE CONFIGURATION AND ORDERING INFORMATION
Each device is available for production in user programmable versions (OTP) as well as in factory coded versions (ROM). OTP devices are shipped to customers with a default content (FFh), while ROM factory coded parts contain the code supplied by the customer. This implies that OTP devices have to be configured by the customer using the Option Bytes while the ROM devices are factory-configured. 14.1 OPTION BYTES The option byte allows the hardware configuration of the microcontroller to be selected. The option byte has no address in the memory
7 FMP Default Value 1 1 1 1 1 1 WDG HALT 1
map and can be accessed only in programming mode (for example using a standard ST7 programming tool). The default content of the OTP is fixed to FFh. This means that all the options have "1" as their default value. In masked ROM devices, the option bytes are fixed in hardware by the ROM code (see option list). For ROM devices, two other options have to be specified in the option list: - LVD enable/disable - Oscillator source selection For OTP devices, LVD is selected by different order codes (see Figure 93) and Oscillator Source selection is not required.
0 WDG SW 1
USER OPTION BYTE
USER OPTION BYTE Bit 7:6,4 = Reserved, must always be 1. Bit 5 = Reserved, must always be 0. Bit 3 = FMP Full memory protection This option bit allows the protection of the software contents against piracy (program or data). When the protection is activated, read-out of the EPROM or data EEPROM contents is prevented by hardware. 0: Read-out protection enabled 1: Read-out protection disabled Bit 2 = Reserved, must always be 1
Bit 1 = WDG HALT Watchdog Reset on HALT This option bit determines if a RESET is generated when entering HALT mode while the Watchdog is active. 0: No Reset generation when entering Halt mode 1: Reset generation when entering Halt mode Bit 0 = WDG SW Hardware or software watchdog This option bit selects the watchdog type. 0: Hardware (watchdog always enabled) 1: Software (watchdog to be enabled by software)
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14.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE Customer code is made up of the ROM contents and the list of the selected options (if any). The ROM contents are to be sent on diskette, or by electronic means, with the S19 hexadecimal file generated by the development tool. All unused bytes must be set to FFh. Figure 92. ROM Factory Coded Device Types
TEMP. DEVICE PACKAGE RANGE X / XXX Code name (defined by STMicroelectronics) = LVD disabled S= LVD enabled 1= standard 0 to +70 C 6= industrial -40 to +85 C 7= automotive -40 to +105 C 3 = automotive -40 to +125 C T= TQFP ST72311R6, ST72311R7, ST72311R9
The selected options are communicated to STMicroelectronics using the correctly completed OPTION LIST appended. The STMicroelectronics Sales Organization will be pleased to provide detailed information on contractual points.
Figure 93. OTP User Programmable Device Types
TEMP. DEVICE PACKAGE RANGE X = LVD disabled S= LVD enabled 1= standard 0 to +70 C 6= industrial -40 to +85 C 7= automotive -40 to +105 C 3 = automotive -40 to +125 C T= TQFP ST72T311R6, ST72T311R7, ST72T311R9 ST72T511R6, ST72T511R7, ST72T511R9 ST72T532R4
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TRANSFER OF CUSTOMER CODE (Cont'd)
ST72311R MICROCONTROLLER OPTION LIST ............................. ............................. ............................. Contact ............................. Phone N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STMicroelectronics references Device: [ ] ST72311R9 [ ] ST72311R7 [ ] ST72311R6 Package: Temperature Range: [ ] TQFP64 [] 0C to + 70C [ ] - 40C to + 85C [ ] - 40C to + 105C [ ] - 40C to + 125C Customer Address
Oscillator Source Selection: [ ] Quartz Crystal/Ceramic resonator [ ] External Clock Watchdog Selection: [ ] Software Activation [ ] Hardware Activation [ ] No Reset [ ] Reset [ ] Disabled [ ] Enabled [ ] Disabled [ ] Enabled:
Watchdog Reset on Halt
Readout Protection:
LVD Reset
Comments : Supply Operating Range in the application: Notes ............................. Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Date ............................. Note: For other sales types (e.g. EPROM or CAN MCUs), please contact your ST Sales Office.
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14.3 DEVELOPMENT TOOLS STMicroelectronics offers a range of hardware the ST7 from third party manufacturers can be oband software development tools for the ST7 microtain from the STMicroelectronics Internet site controller family. Full details of tools available for www.stmcu.com. STMicroelectronics Tools Four types of development tool are offered by ST, all of which connect to a PC via a parallel (LPT) port:
In-Circuit Emulation ST7 Development Kit Yes. (Same features as HDS2 emulator but no trace/ logic analyzer) Programming Capability1) Yes (DIP packages only) Software Included ST7 CD ROM with: - ST7 Assembly toolchain - WGDB7 powerful Source Level Debugger for Win 3.1, Win 95 and NT) - C compiler demo versions - ST Realizer for Win 3.1 and Win 95. - Windows Programming Tools for Win 3.1, Win 95 and NT
ST7 HDS2 Emulator
Yes, powerful emulation features including trace/ logic an- No alyzer No Yes (All packages)
ST7 Programming Board
Note: 1. In Situ Programming (ISP) interface for FLASH devices. Table 27. STMicroelectronics Development Tools
Supported Products ST72311R6, ST72311R7, ST72311R9 ST72511R6, ST72511R7, ST72511R9 ST72532R4 ST7MDT2-DVP2 ST7MDT2-EMU2B Development Kit HDS2 Emulator Programming Board ST7MDT2-EPB2/EU ST7MDT2-EPB2/US ST7MDT2-EPB2/UK
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DEVELOPMENT TOOLS (Cont'd) 14.3.1 Package/socket Footprint Proposal To solder the TQFP64 device directly on the application board, or to solder a socket for connecting the emulator probe, the application board should provide the footprint described in Figure 94. This footprint allows both configurations:
s s
Direct TQFP64 soldering YAMAICHI IC149-064-008-S5 socket soldering to plug either the emulator probe or an adaptor board with an TQFP64 clamshell socket. This socket is not compatible with TQFP64 package.
Figure 94. TQFP64 Device And Emulator Probe Compatible Footprint
SK E E1 E3
B E Dim Min Typ Max Min Typ Max mm inches
0.35 0.45 0.50 0.014 0.018 0.020 20.80 14.00 0.819 0.551
e
E1
E3 11.90 12.00 12.10 0.468 0.472 0.476
E1
SK
E3
B
SOCKET
e SK*
0.75 0.80 0.85 0.029 0.031 0.033 26 1.023 Number of Pins
E
DETAIL
N
64 (4x16)
* SK: Plastic socket overall dimensions.
Table 28. Suggested List of TQFP64 Socket Types
Package / Probe TQFP64 EMU PROBE YAMAICHI YAMAICHI Adaptor / Socket Reference IC51-0644-1240.KS-14584 IC149-064-008-S5 SMC Socket type Clamshell
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14.4 ST7 APPLICATION NOTES
IDENTIFICATION DESCRIPTION EXAMPLE DRIVERS AN 969 SCI COMMUNICATION BETWEEN ST7 AND PC AN 970 SPI COMMUNICATION BETWEEN ST7 AND EEPROM AN 971 IC COMMUNICATING BETWEEN ST7 AND M24CXX EEPROM AN 972 ST7 SOFTWARE SPI MASTER COMMUNICATION AN 973 SCI SOFTWARE COMMUNICATION WITH A PC USING ST72251 16-BIT TIMER AN 974 REAL TIME CLOCK WITH ST7 TIMER OUTPUT COMPARE AN 976 DRIVING A BUZZER THROUGH ST7 TIMER PWM FUNCTION AN 979 DRIVING AN ANALOG KEYBOARD WITH THE ST7 ADC AN 980 ST7 KEYPAD DECODING TECHNIQUES, IMPLEMENTING WAKE-UP ON KEYSTROKE AN1017 USING THE ST7 UNIVERSAL SERIAL BUS MICROCONTROLLER AN1041 USING ST7 PWM SIGNAL TO GENERATE ANALOG OUTPUT (SINUSOID) AN1042 ST7 ROUTINE FOR IC SLAVE MODE MANAGEMENT AN1044 MULTIPLE INTERRUPT SOURCES MANAGEMENT FOR ST7 MCUS AN1045 ST7 S/W IMPLEMENTATION OF IC BUS MASTER AN1046 UART EMULATION SOFTWARE AN1047 MANAGING RECEPTION ERRORS WITH THE ST7 SCI PERIPHERALS AN1048 ST7 SOFTWARE LCD DRIVER AN1078 PWM DUTY CYCLE SWITCH IMPLEMENTING TRUE 0% & 100% DUTY CYCLE AN1082 DESCRIPTION OF THE ST72141 MOTOR CONTROL PERIPHERAL REGISTERS AN1083 ST72141 BLDC MOTOR CONTROL SOFTWARE AND FLOWCHART EXAMPLE AN1105 ST7 PCAN PERIPHERAL DRIVER AN1129 PERMANENT MAGNET DC MOTOR DRIVE. AN INTRODUCTION TO SENSORLESS BRUSHLESS DC MOTOR DRIVE APPLICATIONS AN1130 WITH THE ST72141 AN1148 USING THE ST7263 FOR DESIGNING A USB MOUSE AN1149 HANDLING SUSPEND MODE ON A USB MOUSE AN1180 USING THE ST7263 KIT TO IMPLEMENT A USB GAME PAD AN1276 BLDC MOTOR START ROUTINE FOR THE ST72141 MICROCONTROLLER AN1321 USING THE ST72141 MOTOR CONTROL MCU IN SENSOR MODE AN1325 USING THE ST7 USB LOW-SPEED FIRMWARE V4.X AN1445 USING THE ST7 SPI TO EMULATE A 16-BIT SLAVE AN1475 DEVELOPING AN ST7265X MASS STORAGE APPLICATION AN1504 STARTING A PWM SIGNAL DIRECTLY AT HIGH LEVEL USING THE ST7 16-BIT TIMER PRODUCT EVALUATION AN 910 PERFORMANCE BENCHMARKING AN 990 ST7 BENEFITS VERSUS INDUSTRY STANDARD AN1077 OVERVIEW OF ENHANCED CAN CONTROLLERS FOR ST7 AND ST9 MCUS AN1086 U435 CAN-DO SOLUTIONS FOR CAR MULTIPLEXING AN1150 BENCHMARK ST72 VS PC16 AN1151 PERFORMANCE COMPARISON BETWEEN ST72254 & PC16F876 AN1278 LIN (LOCAL INTERCONNECT NETWORK) SOLUTIONS PRODUCT MIGRATION AN1131 MIGRATING APPLICATIONS FROM ST72511/311/214/124 TO ST72521/321/324 AN1322 MIGRATING AN APPLICATION FROM ST7263 REV.B TO ST7263B AN1365 GUIDELINES FOR MIGRATING ST72C254 APPLICATION TO ST72F264 PRODUCT OPTIMIZATION
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DESCRIPTION USING ST7 WITH CERAMIC RESONATOR HOW TO MINIMIZE THE ST7 POWER CONSUMPTION SOFTWARE TECHNIQUES FOR IMPROVING MICROCONTROLLER EMC PERFORMANCE MONITORING THE VBUS SIGNAL FOR USB SELF-POWERED DEVICES ST7 CHECKSUM SELF-CHECKING CAPABILITY CALIBRATING THE RC OSCILLATOR OF THE ST7FLITE0 MCU USING THE MAINS EMULATED DATA EEPROM WITH XFLASH MEMORY EMULATED DATA EEPROM WITH ST7 HDFLASH MEMORY EXTENDING THE CURRENT & VOLTAGE CAPABILITY ON THE ST7265 VDDF SUPPLY ACCURATE TIMEBASE FOR LOW-COST ST7 APPLICATIONS WITH INTERNAL RC OSCILAN1530 LATOR PROGRAMMING AND TOOLS AN 978 KEY FEATURES OF THE STVD7 ST7 VISUAL DEBUG PACKAGE AN 983 KEY FEATURES OF THE COSMIC ST7 C-COMPILER PACKAGE AN 985 EXECUTING CODE IN ST7 RAM AN 986 USING THE INDIRECT ADDRESSING MODE WITH ST7 AN 987 ST7 SERIAL TEST CONTROLLER PROGRAMMING AN 988 STARTING WITH ST7 ASSEMBLY TOOL CHAIN AN 989 GETTING STARTED WITH THE ST7 HIWARE C TOOLCHAIN AN1039 ST7 MATH UTILITY ROUTINES AN1064 WRITING OPTIMIZED HIWARE C LANGUAGE FOR ST7 AN1071 HALF DUPLEX USB-TO-SERIAL BRIDGE USING THE ST72611 USB MICROCONTROLLER AN1106 TRANSLATING ASSEMBLY CODE FROM HC05 TO ST7 PROGRAMMING ST7 FLASH MICROCONTROLLERS IN REMOTE ISP MODE (IN-SITU PROAN1179 GRAMMING) AN1446 USING THE ST72521 EMULATOR TO DEBUG A ST72324 TARGET APPLICATION AN1478 PORTING AN ST7 PANTA PROJECT TO CODEWARRIOR IDE AN1527 DEVELOPING A USB SMARTCARD READER WITH ST7SCR AN1575 ON-BOARD PROGRAMMING METHODS FOR XFLASH AND HDFLASH ST7 MCUS
IDENTIFICATION AN 982 AN1014 AN1015 AN1040 AN1070 AN1324 AN1477 AN1502 AN1529
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15 SUMMARY OF CHANGES
Description of the changes between the current release of the specification and the previous one.
Revision 2.7 Changed Figure 80 Changed Watchdog and Halt mode Option to read "Watchdog reset on Halt" in Section 14. Main Changes Date April-03
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Notes:
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c)2003 STMicroelectronics - All Rights Reserved. Purchase of I2C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips. STMicroelectronics Group of Companies Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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